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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
FREEDMTM-336A1024
FRAME ENGINE AND DATALINK MANAGER 336A1024
DATASHEET
PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 7: FEBRUARY, 2002
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE
I
PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
CONTENTS 1 2 3 4 5 6 7 8 9 10 ACRONYMS .............................................................................................1 FEATURES...............................................................................................3 REFERENCES .........................................................................................9 APPLICATIONS......................................................................................10 APPLICATION EXAMPLES .................................................................... 11 BLOCK DIAGRAM..................................................................................12 DESCRIPTION .......................................................................................13 PIN DIAGRAM ........................................................................................14 PIN DESCRIPTION ................................................................................15 FUNCTIONAL DESCRIPTION ...............................................................64 10.1 INTERFACES ..............................................................................64 10.1.1 10.1.2 10.2 SCALEABLE BANDWIDTH INTERCONNECT (SBI) INTERFACE...................................................................64 ANY-PHY INTERFACE ..................................................65
MEMORY PORT ..........................................................................75 10.2.1 10.2.2 WRITING .......................................................................75 READING ......................................................................76
10.3
PACKET WALKTHROUGH..........................................................76 10.3.1 10.3.2 INGRESS PATH ............................................................76 EGRESS PATH..............................................................79
10.4
LOOPBACK .................................................................................80 10.4.1 10.4.2 CLOCK AND DATA LOOPBACK ...................................80 SBI LINE LOOPBACK ...................................................80
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
10.4.3 10.5
SYSTEM SIDE LOOPBACK ..........................................80
INITIALIZATION PROCESS ........................................................81 10.5.1 10.5.2 CB AND RS MEMORY FPP INITIALIZATION................81 CONNECTION INITIALIZATION FOR SEQUENCED LINKS ............................................................................81
10.6 10.7 10.8 10.9
ANY-PHY TEAR DOWN PROCEDURE.......................................82 CI TEAR DOWN PROCEDURE...................................................82 RESTRICTIONS ON ANY-PHY TO CI MAPPING........................83 BLOCK DESCRIPTIONS .............................................................84 10.9.1 10.9.2 10.9.3 10.9.4 10.9.5 10.9.6 10.9.7 10.9.8 10.9.9 EXTRACT SCALEABLE BANDWIDTH INTERCONNECT (EXSBI336)....................................................................84 RECEIVE CHANNEL ASSIGNOR (RCAS-12)...............84 RECEIVE HDLC PROTOCOL ENGINE (RHDL-12) ......86 RECEIVE FRAGMENT BUILDER (RFRAG)..................89 FRAME BUILDER (FRMBLD)........................................93 INGRESS QUEUE MANAGER (IQM-12) ......................99 RECEIVE ANY-PHY INTERFACE (RAPI-12).................99 TRANSMIT ANY-PHY INTERFACE (TAPI-12).............100 TRANSMIT FRAGMENTOR (TFRAG).........................102
10.9.10 CB_DRAMC.................................................................105 10.9.11 RS_DRAMC.................................................................105 10.9.12 SRAMC........................................................................107 10.9.13 TRANSMIT HDLC PROCESSOR (THDL-12) .............. 111 10.9.14 TRANSMIT CHANNEL ASSIGNOR (TCAS-12)........... 115 10.9.15 SBI INSERTER............................................................ 117
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
10.9.16 PERFORMANCE MONITOR ....................................... 117 10.9.17 DIGITAL DELAY LOCK LOOP (DDLL)......................... 119 10.9.18 JTAG TEST ACCESS PORT ....................................... 119 10.9.19 MICROPROCESSOR INTERFACE............................. 119 11 NORMAL MODE REGISTER DESCRIPTION ......................................125 11.1 11.2 MICROPROCESSOR ACCESSIBLE REGISTERS ...................125 MICROPROCESSOR ACCESSIBLE MEMORIES ....................290 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 12 PM-12 MEMORY MAP ................................................290 EQM-12 MEMORY ......................................................294 TFRAG ANY-PHY CHANNEL RAM MEMORY MAP....296 RFRAG MEMORY MAP...............................................297 RE-SEQUENCE STRUCTURES (RS) MEMORY MAP301 CHUNK BUFFER MEMORY MAP ...............................308 CONNECTION CONTEXT (CC) MEMORY MAP ........312
TEST FEATURES DESCRIPTION .......................................................316 12.1 12.2 TEST MODE REGISTERS ........................................................316 JTAG TEST PORT .....................................................................317 12.2.1 IDENTIFICATION REGISTER .....................................318
13
OPERATIONS ......................................................................................319 13.1 JTAG SUPPORT........................................................................319
14
FUNCTIONAL TIMING .........................................................................325 14.1 14.2 14.3 SBI DROP BUS INTERFACE TIMING .......................................325 SBI ADD BUS INTERFACE TIMING ..........................................326 RECEIVE LINK TIMING.............................................................326
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
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14.4 14.5 14.6 14.7 14.8 14.9
TRANSMIT LINK TIMING ..........................................................327 RECEIVE APPI TIMING (ANY-PHY LEVEL 2) ...........................327 TRANSMIT APPI TIMING (ANY-PHY LEVEL 2) ........................331 RECEIVE APPI TIMING (ANY-PHY LEVEL 3) ...........................334 TRANSMIT APPI TIMING (ANY-PHY LEVEL 3) ........................335 RE-SEQUENCING SDRAM INTERFACE..................................337
14.10 CHUNK BUFFER SDRAM INTERFACE ....................................338 14.11 CONTEXT SSRAM INTERFACE (ZBT SSRAM MODE)............339 14.12 MICROPROCESSOR INTERFACE ...........................................340 15 16 17 ABSOLUTE MAXIMUM RATINGS........................................................343 D.C. CHARACTERISTICS....................................................................344 FREEDM-336A1024 TIMING CHARACTERISTICS.............................346 17.1 17.2 17.3 17.4 17.5 17.6 17.7 18 19 SBI BUS INTERFACE TIMING ..................................................346 SBI ADD BUS INTERFACE TIMING ..........................................348 SERIAL CLOCK AND DATA TIMING .........................................350 ANY-PHY TIMING ......................................................................352 MICROPROCESSOR TIMING...................................................355 MEMORY TIMING......................................................................356 JTAG TIMING.............................................................................358
ORDERING AND THERMAL INFORMATION ......................................359 520 PIN SBGA - 40 X 40 MM BODY....................................................360
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
LIST OF FIGURES FIGURE 1 FIGURE 2 FIGURE 3 - AN OC-12 ACCESS CARD FOR A ROUTER ............................ 11 - THE BLOCK DIAGRAM OF FREEDM-336A1024 .....................12 - ANY-PHY LEVEL 2 MODE SEGMENT TRANSFER - NON SEQUENCED DATAGRAMS ON A LINK SUPPORTING SEQUENCING (I.E. CONTROL, LCP, NCP PACKETS) (INGRESS AND EGRESS) ............................................................................66 - ANY-PHY LEVEL 2 MODE SEGMENT TRANSFER - NONHEADER SEGMENT (I.E. NOT FIRST SEGMENT OF A DATAGRAM) OR TRANSPARENT MODE (INGRESS AND EGRESS).....................................................................................67 - ANY-PHY LEVEL 2 MODE HEADER SEGMENT - PPP OVER SEQUENCED LINK (INGRESS AND EGRESS)..........................68 - ANY-PHY LEVEL 2 MODE HEADER SEGMENT - FR OVER SEQUENCED LINK (INGRESS AND EGRESS)..........................69 - ANY-PHY LEVEL 2 MODE HEADER SEGMENT - ML- PPP WITH FRAGMENTS OUT (INGRESS ONLY)..............................70 - ANY-PHY LEVEL 2 MODE HEADER SEGMENT - PPP OVER A SEQUENCED LINK WITH ADDRESS AND CONTROL FIELD HEADER COMPRESSION (INGRESS AND EGRESS)...............71 - ANY-PHY LEVEL 2 MODE HEADER SEGMENT - PPP OVER A SEQUENCED LINK WITH PID HEADER COMPRESSION (INGRESS AND EGRESS) ..........................................................72
FIGURE 4
FIGURE 5 FIGURE 6 FIGURE 7 FIGURE 8
FIGURE 9
FIGURE 10 - ANY-PHY LEVEL 2 MODE HEADER SEGMENT - PPP OVER A SEQUENCED LINK WITH ADDRESS /CONTROL FIELD AND PID HEADER COMPRESSION (INGRESS AND EGRESS)...............73 FIGURE 11 - ANY-PHY LEVEL 3 MODE SEGMENT - TRANSPARENT OR NON-HEADER SEGMENT (INGRESS AND EGRESS)...............74 FIGURE 12 - ANY-PHY LEVEL 3 MODE HEADER SEGMENT - FR OVER A SEQUENCED LINK (INGRESS AND EGRESS)..........................75 FIGURE 13 - INGRESS DATA FLOW .............................................................77
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
FIGURE 14 - EGRESS DATA FLOW ..............................................................79 FIGURE 15 - HDLC FRAME............................................................................86 FIGURE 16 - CRC GENERATOR....................................................................87 FIGURE 17 - PARTIAL PACKET BUFFER STRUCTURE ...............................88 FIGURE 18 - ENCAPSULATED CHUNK STRUCTURES ...............................92 FIGURE 19 - LINKED LIST DATA STRUCTURE OF A DATAGRAM...............93 FIGURE 20 - THE ELEMENTS IN THE RE-SEQUENCING BLOCK ..............94 FIGURE 21 - THE 14-BIT SLIDING WINDOW USED FOR RE-SEQUENCING .....................................................................................................96 FIGURE 22 - THE ELEMENTS IN THE RE-SEQUENCING BLOCK ..............97 FIGURE 23 - THE INGRESS QUEUE MANAGER BLOCK.............................99 FIGURE 24 - ENCAPSULATED CHUNK STRUCTURE ...............................103 FIGURE 25 - LINKED LIST DATA STRUCTURE OF A DATAGRAM.............104 FIGURE 26 - DRAM CONFIGURATION FOR THE CHUNK BUFFER INTERFACE ...............................................................................106 FIGURE 27 - DRAM CONFIGURATION FOR THE RE-SEQUENCING MEMORY INTERFACE ..............................................................107 FIGURE 28 - 4 BANK CONFIGURATION FOR 8 MB OF ZBT OR STANDARD SSRAM ......................................................................................108 FIGURE 29 - 2 BANKS CONFIGURATION FOR 8 M BITS OF ZBTCOMPATIBLE OR STANDARD SSRAM....................................109 FIGURE 30 - 1 BANK CONFIGURATION FOR 8 M BITS OF ZBT OR STANDARD SSRAM.................................................................. 110 FIGURE 31 - PARTIAL PACKET BUFFER STRUCTURE ............................. 112 FIGURE 32 - BOUNDARY SCAN ARCHITECTURE .....................................319 FIGURE 33 - TAP CONTROLLER FINITE STATE MACHINE.......................321 FIGURE 34 - T1/E1 DROP BUS FUNCTIONAL TIMING ..............................325
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE VIII
PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
FIGURE 35 - DS3 DROP BUS FUNCTIONAL TIMING .................................325 FIGURE 36 - DS3 ADD BUS ADJUSTMENT REQUEST FUNCTIONAL TIMING326 FIGURE 37 - RECEIVE LINK TIMING...........................................................327 FIGURE 38 - TRANSMIT LINK TIMING ........................................................327 FIGURE 39 - RECEIVE APPI TIMING (NORMAL TRANSFER 16 BIT 52 MHZ) ...................................................................................................328 FIGURE 40 - RECEIVE APPI TIMING (AUTO DESELECTION) ...................329 FIGURE 41 - RECEIVE APPI TIMING (OPTIMAL RESELECTION) .............330 FIGURE 42 - RECEIVE APPI TIMING (BOUNDARY CONDITION) ..............331 FIGURE 43 - TRANSMIT APPI TIMING (NORMAL TRANSFER) .................332 FIGURE 44 - TRANSMIT APPI TIMING (SPECIAL CONDITIONS) ..............333 FIGURE 45 - TRANSMIT APPI POLL TIMING ..............................................334 FIGURE 46 - RECEIVE APPI TIMING (NORMAL TRANSFER 8 BIT 104 MHZ) ...................................................................................................334 FIGURE 47 - TRANSMIT APPI TIMING ANY-PHY LEVEL 3 (NORMAL TRANSFER) ..............................................................................335 FIGURE 48 - TRANSMIT APPI TIMING ANY-PHY LEVEL 3 (SPECIAL CONDITION)..............................................................................336 FIGURE 49 - TRANSMIT APPI POLLING TIMING (ANY-PHY LEVEL 3)......337 FIGURE 50 - READ TIMING FOR RE-SEQUENCING MEMORY.................338 FIGURE 51 - WRITE TIMING RE-SEQUENCING MEMORY .......................338 FIGURE 52 - READ TIMING FOR CHUNK BUFFER MEMORY ...................339 FIGURE 53 - WRITE TIMING FOR CHUNK BUFFER MEMORY .................339 FIGURE 54 - READ FOLLOWED BY WRITE TIMING FOR ZBT MODE......339 FIGURE 55 - READ FOLLOWED BY WRITE TIMING FOR STANDARD SSRAM MODE...........................................................................340
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
FIGURE 56 - READ AND WRITE TO NON-BURSTABLE REGISTER SPACE ...................................................................................................340 FIGURE 57 READ AND WRITE TO BURSTABLE ADDRESS SPACE ...........341 FIGURE 58 - CONSECUTIVE WRITE ACCESSES USING WRDONEB......342 FIGURE 59 - SBI336 DROP BUS INPUT INTERFACE TIMING ...................347 FIGURE 60 - SBI336 ADD BUS INPUT INTERFACE TIMING ......................348 FIGURE 61 - SBI336 ADD BUS OUTPUT INTERFACE TIMING ..................349 FIGURE 62 - SBI ADD BUS COLLISION AVOIDANCE TIMING ...................349 FIGURE 63 - RECEIVE DATA TIMING..........................................................351 FIGURE 64 - TRANSMIT DATA TIMING .......................................................351 FIGURE 65 - RECEIVE ANY-PHY INTERFACE TIMING ..............................354 FIGURE 66 - TRANSMIT ANY-PHY INTERFACE TIMING............................355 FIGURE 67 - SYNCHRONOUS I/O TIMING .................................................356 FIGURE 68 - JTAG PORT INTERFACE TIMING ..........................................358 FIGURE 69 - 520 PIN ENHANCED BALL GRID ARRAY (SBGA) .................360
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 TABLE 10 TABLE 11 TABLE 12 TABLE 13 TABLE 14 TABLE 15 TABLE 16 TABLE 17 TABLE 18 TABLE 19 TABLE 20 TABLE 21 - TERMINOLOGY ..........................................................................1 - SBI INTERFACE SIGNALS (30 PINS).......................................15 - CLOCK/DATA INTERFACE SIGNALS (48 PINS) ......................22 - ANY-PHY PACKET INTERFACE SIGNALS (70 PINS) ..............24 - RE-SEQUENCING SDRAM INTERFACE (52 SIGNALS)..........44 - CONTEXT MEMORY SYNCHRONOUS SSRAM INTERFACE (57 SIGNALS) ....................................................................................47 - CHUNK BUFFER SDRAM INTERFACE (67 SIGNALS) ............49 - MICROPROCESSOR INTERFACE SIGNALS (44) ...................52 - MISCELLANEOUS INTERFACE SIGNALS (10 PINS) ..............57 - POWER AND GROUND SIGNALS ...........................................59 - SBI SPE/TRIBUTARY TO RCAS LINK MAPPING.....................84 - DEFINITIONS .......................................................................... 114 - THDL CONFIGURATION FOR SINGLE DATA RATE CHANNELS ................................................................................................... 115 - SBI-SPE TRIBUTARY TO TCAS LINK MAPPING ................... 116 - NORMAL MODE MICROPROCESSOR ACCESSIBLE REGISTERS MEMORY MAP..................................................... 119 - MEMORY MODE CONFIGURATION ......................................127 - SBI MODE ...............................................................................152 - SERIAL LINK TO SBI LINK MAPPING ....................................159 - RESERVED BIT SETTINGS....................................................166 - CRC[1:0] SETTINGS ...............................................................166 - CRC[1:0] SETTINGS ...............................................................176
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
TABLE 22 TABLE 23 TABLE 24 TABLE 25 TABLE 26 TABLE 27 TABLE 28 TABLE 29 TABLE 30 TABLE 31 TABLE 32 TABLE 33 TABLE 34 TABLE 35 TABLE 36 TABLE 37 TABLE 38 TABLE 39 TABLE 40 TABLE 41 TABLE 42 TABLE 43 TABLE 44 TABLE 45
- FLAG[2:0] SETTINGS .............................................................181 - LEVEL[3:0]/TRANS SETTINGS ..............................................183 - SBI MODE ...............................................................................195 - SERIAL LINK TO SBI LINK MAPPING ....................................203 - ANY-PHY ENCODING .............................................................206 - RESERVED/UNUSED BIT SETTINGS....................................210 - TRIB_TYP ENCODING............................................................213 - SBI EXTRACT SPE_TYP[2:0] .................................................215 - SBI EXTRACT SPE_TYP[2:0] .................................................217 - SBI EXTRACT SPE_TYP[2:0] .................................................219 - SBI EXTRACT SPE_TYP[2:0] .................................................221 - ANY-PHY ENCODING .............................................................223 - VALID BLEN ............................................................................227 - TRIB_TYP ENCODING............................................................239 - SBI INSERT SPE_TYP[2:0].....................................................240 - SBI INSERT SPE_TYP[2:0].....................................................242 - SBI INSERT SPE_TYP[2:0].....................................................244 - SBI INSERT SPE_TYP[2:0].....................................................247 - MPMEMSELECT FUNCTION..................................................249 - MPBURSTLENGTH FUNCTION .............................................249 - MPCOMMAND FUNCTIONS...................................................250 - PM-12 MEMORY MAP.............................................................291 - EQM-12 MEMORY MAP..........................................................294 - TFRAG ANY-PHY CHANNEL RAM MEMORY MAP ................296
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
TABLE 46 TABLE 47 TABLE 48 TABLE 49 TABLE 50 TABLE 51 TABLE 52 TABLE 53 TABLE 54 TABLE 55 TABLE 56 TABLE 57 TABLE 58 TABLE 59 TABLE 60 TABLE 61 TABLE 62 TABLE 63 TABLE 64 TABLE 65 TABLE 66
- RFRAG MEMORY MAP...........................................................298 - RS MEMORY MAP ..................................................................302 - SEQUENCED CONNECTION IDENTIFIER LOOKUP RECORD ...................................................................................................305 - NON-SEQUENCED CONNECTION IDENTIFICATION LOOKUP RECORD ...................................................................................305 - CONTROL CONNECTION IDENTIFIER LOOKUP RECORD .306 - CORRUPT CONNECTION IDENTIFIER LOOKUP RECORD .306 -LSB RECORDS STATUS RECORD .........................................306 -MSB RECORDS RECORD.......................................................307 - LSB RECORD FREELIST RECORD .......................................307 - CHUNK BUFFER MEMORY MAP (ONLY EVEN ADDRESSES ARE VALID) ...............................................................................309 - CONNECTION CONTEXT MEMORY ADDRESSING .............312 - CC MEMORY MAP ..................................................................313 - TEST MODE REGISTER MEMORY MAP ...............................317 - INSTRUCTION REGISTER .....................................................317 - FREEDM-336A1024 ABSOLUTE MAXIMUM RATINGS .........343 - FREEDM-336A1024 D.C. CHARACTERISTICS .....................344 - REFCLK TIMING .....................................................................346 - SBI336 DROP BUS INPUT TIMING (REFERENCED TO (FIGURE 59)).............................................................................................347 - SBI336 ADD BUS INPUT TIMING (REFERENCED TO FIGURE 60 ).............................................................................................348 - SBI336 ADD BUS OUTPUT TIMING (REFERENCED TO (FIGURE 61 AND FIGURE 62)) .................................................349 - CLOCK/DATA INPUT (FIGURE 37) .........................................350
XIII
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
TABLE 67 TABLE 68 TABLE 69 TABLE 70 TABLE 71 TABLE 72 TABLE 73 TABLE 74 TABLE 75 TABLE 76 TABLE 77 TABLE 78 TABLE 79
- CLOCK/DATA OUTPUT (FIGURE 38) .....................................351 - ANY-PHY LEVEL 2 INTERFACE (FIGURE 65 AND FIGURE 66) ...................................................................................................352 - ANY-PHY LEVEL 3 INTERFACE (FIGURE 65 AND FIGURE 66) ...................................................................................................353 - MICROPROCESSOR INTERFACE (FIGURE 67) ...................355 - SYSCLK TIMING .....................................................................356 - RESEQUENCING SDRAM INTERFACE (FIGURE 67) ...........356 - CHUNK BUFFER SDRAM INTERFACE (FIGURE 67) ............357 - CONNECTION CONTEXT MEMORY SSRAM INTERFACE (FIGURE 67) ..............................................................................357 - JTAG PORT INTERFACE (FIGURE 68) ..................................358 - FREEDM-336A1024 ORDERING INFORMATION ..................359 - FREEDM-336A1024 THETA JC...............................................359 - FREEDM-336A1024 JUNCTION TEMP ..................................359 - FREEDM-336A1024 THETA JA VS. AIRFLOW .......................359
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ACRONYMS Table 1 - Terminology Definition The Address Field in a PPP header Saturn Interface Specification and Interoperability Framework for Packet and Cell transfers between Physical layer and Link Layer devices ANY-PHY Packet Interface The Begin bit of a fragment Backward Explicit Congestion Notification Command/Response bit in the Q.922 Header Connection Identifier Cyclic Redundancy Check Cyclic Redundancy Check as specified by the CCITT Control field in a PPP header Class of Service A fragment, packet or frame Discard Eligibility Digital Delay Lock Loop Digital Subscriber Loop Access Multiplexor The End bit of a fragment Error Code Error Correcting Code Traffic flow from the switch to the line is defined as Egress traffic - equivalent to transmit End of Packet Forward Explicit Congestion Notification First In First Out Frame Check Sequence Frame Relay
Term ADDR ANY-PHY APPI B BECN C/R CI CRC CRC-CCITT CNTL COS Datagram DE DLL DSLAM E EC ECC Egress EOP FECN FIFO FCS FR
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
Term Fragment Frame FUNI HDLC HCS Ingress IETF MIB ML ML-FR ML-PPP MTU MRU Packet PID PPP Q.922 RFC SBI SBI336 SDRAM SN SPE SSRAM TM ZBT
Definition A sub-unit of a packet of frame A Frame Relay unit of transfer Frame Relay User to Network Interface High level Data Link Control Header Check Sequence Traffic flow from the line side to switch is defined as Ingress traffic - equivalent to receive Internet Engineering Task Force Management Information Database Multilink Multilink Frame Relay Multilink PPP Maximum Transfer Unit Maximum Receive Unit An IP data unit Process ID field in a PPP header Point to Point Protocol ISDN Data Link Layer Specification for Frame Mode Bearer Services Request For Comments Scalable Bandwidth Interface A Scalable Bandwidth Interface operating at 77.76 MHz capable of supporting 336 T1 links Synchronous Dynamic Random Access Memory Sequence Number Synchronous Payload Envelop Synchronous Static Random Access Memory Traffic Management Zero Bus Turnaround
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
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FEATURES * Single-chip multi-channel HDLC controller with either a 52 MHz 16 bit ANYPHY Level 2 or a 104 MHz 8 bit ANY-PHY Level 3 packet interface for transfer of packet, frame or fragment data using an external controller. Supports line rate throughput for 336 T1s, 252 E1s, or 12 DS-3s. (40 byte packets encapsulated in PPP over HDLC (50 byte transfers (RFC 1661) or 55 byte transfers (RFC 1990)). Provides simultaneous support of PPP, Frame Relay, multilink-PPP and multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure.
*
*
Interfaces * A 52MHz, 16-bit ANY-PHY Level 2 or 104MHz, 8-bit ANY-PHY Level 3 packet interface for system side connection. * * * * * * * * * The interface is capable of supporting full datagram transfer on a per ANY-PHY channel basis or Fragmented packets or frames on a per ANY-PHY channel basis.
A single 77 MHz SBI (SBI336) interface. Up to four 19.44 MHz SBI buses may be supported if external glue logic is used. 12 separate clock and data interfaces to support 12 links of arbitrary data rate up to 52MHz (e.g., DS3/E3). A 100 MHz, 48-bit SDRAM interface for ingress and egress per packet/fragment storage. A 100 MHz, 32-bit SDRAM interface for ingress re-sequencing data structures. A 100 MHz, 36-bit SSRAM interface for Ingress/Egress Context storage. The device provides the standard 5 signal P1149.1 JTAG test port for boundary scan. A 32-bit microprocessor interface for configuration and status monitoring.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Channelization/HDLC Features * Support for up to1024 HDLC channels in both the ingress and egress direction, with individual HDLC channel speeds ranging from 56Kbps to 52 Mbps (682 CH's for any arbitrary combination of link rates). The 1024 HDLC channels can be assigned to a mixture of physical links via the SBI336 interface. The SBI336 transports the equivalent of 12 STS-1 synchronous payload envelopes (SPE). Each STS-1 SPE can be individually configured to carry 28 T1/J1s, 21 E1s, 1 DS3 or 1 fractional DS3/E3 link. Supports 12 individual clock and data interfaces that can individually operate at up to 52 MHz. The device can be configured to process data from either the clock and data interfaces or from the SBI336 on a per clock-data-link/SPE basis. In a channelized application, the number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1). For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences. For each HDLC channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. For each HDLC channel, time-slots are selectable to be in 56 Kbps format or 64 Kbps clear channel format. For each HDLC channel, the HDLC transmitter supports programmable flag sequence generation, bit stuffing and frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the external TM engine or automatically when the channel underflows.
*
*
* *
* * *
PPP Features * * Link Control protocol packet identification. Packets are identified by the PID as control protocols and will be forwarded to the ANY-PHY interface. Capable of supporting line rate transfers of packet sizes from 40 to 9.6K bytes.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
*
Support for PPP header compression as per RFC 1661 on sequenced links. On receive, compressed headers are detected and processed appropriately as they arrive on an HDLC channel. Compressed PPP headers are passed to the system side via the ANY-PHY interface. On transmit, compressed headers are accepted from the system side device via the ANY-PHY interface. On sequenced links, all required processing is provided to correctly insert the compressed PPP headers into the 1024 HDLC channels. On unsequenced links, header compression is only supported through the use of transparent mode. Multilink PPP bundles: * * Capable of supporting fragment sizes from 2 to 9.6K bytes with the restriction that the maximum number of fragments per packet is 81. Support for 3 egress fragmentation sizes (128, 256, and 512 bytes) configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle basis. The Freedm-336A1024 supports header compression but does not perform it. Either 12 bit or 24bit sequence number, with short and long fragment header formats, is supported. Supports 168 bundles in ingress direction. These bundles are composed of independent HDLC channels. Supports 168 bundles in egress direction. These bundles are composed of independent HDLC channels. Support for fragmentation on a single HDLC channel. Support for 16 COS levels in accordance with RFC 2686. Support for up to 100ms of intra bundle skew in the receive direction when supporting the minimum fragment size. Capable of supporting larger skews (<400ms) with larger fragment sizes. The intra-bundle skew is limited by 12 bit sequence number capabilities. Up to 12 member links per bundle. * Each member link is required to operate at the same speed. Either T1/J1 or E1 rates.
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* * * * * *
*
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Frame Relay Features * Link layer address lookup can be performed based on HDLC channel and DLCI for HDLC channels supporting Frame Relay protocols. Optionally, the lookup can be performed on a per HDLC channel basis. Capable of supporting line rate transfers of frame sizes from 40 to 9.6K bytes. Multilink FR bundles and FRF.12 UNI and NNI (not End-to-End) fragmentation: * * Capable of supporting fragment sizes from 2 to 9.6K with the restriction that the maximum number of fragments per packet is 81. 10 bit DLCI format supported for channels requiring DLCI lookup. Alternative DLCI formats supported when the lookup is based on HDLC channel only. The lookup algorithm can support a maximum of 16K connection identifiers (CIs) amongst multilink FR bundles. The connection identifiers are ignored in singlelink FR channels. Control frames are identified and forwarded to ANY-PHY interface Support for 3 egress fragmentation sizes (128, 256, and 512 bytes) configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle basis. 12 bit sequence numbers supported. Support for fragmentation on a single HDLC channel. 168 bundles in ingress direction. These bundles are composed of independent HDLC channels. 168 bundles in egress direction. These bundles are composed of independent HDLC channels. Support for up to 100ms intra-bundle skew within the limits of 12 bit sequence number capabilities when supporting the minimum fragment size. Capable of supporting larger skews (<400ms) with larger fragment sizes. Up to 12 member links per bundle.
* *
*
* *
* * * * *
*
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FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
* *
Each member link operates at the same speed either T1/J1 or E1. FECN, BECN, and DE ingress processing as per FRF.12. The C/R value passed out in frame out mode is the value received on the Begin fragment.
Statistics * FREEDM-336A1024 maintains a suite of counters based on HDLC channels. These counters include: * * * * * * * CRC Errors observed by the HDLC framer. HDLC framing aborts. Non-Octet aligned frames. HDLC MRU exceeded. Bytes and datagrams received. Bytes and datagrams transmitted.
Additionally, the FREEDM-336A1024 provides the following global error counters: * Number of bytes discarded due to transmit overflows, receive overflows in the presence of link failures, and line rate arrivals of small (< 40 byte) packets. Number of Lost fragment events FIFO overflows and underruns. Additional error states are also tracked.
* * * *
Additionally, FREEDM-336A1024 supports the MFR MIB by detecting and informing the host of unexpected sequence numbers and time outs.
Fault Isolation Features * * Three levels of loopback are provided: Twelve Clock and Data line loopbacks
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
* *
SBI336 tributary loopback System side loopback per HDLC channel.
Technologies * * * 520 pin (1.27 mil pitch) enhanced ball grid array (SBGA) package. 376 signal pins, 3.3V I/O. Low power 0.18mm CMOS technology using 1.8V core power.
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FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
3
REFERENCES PPP 1. RFC 1661, The Point-to-Point Protocol (PPP). 2. RFC 1990, PPP Multilink Protocol. 3. RFC-2686, Multiclass Multilink PPP. Frame Relay 1. ANSI T1.617a-1994, Annex F. 2. RFC 1490, Multiprotocol Interconnect over Frame Relay. 3. FRF.1.1, User-to-Network (UNI) Implementation Agreement. 4. FRF.3.1, Multiprotocol Encapsulation Implementation Agreement (MEI). 5. FRF.4.1, Frame Relay User-to-Network SVC Implementation Agreement. 6. FRF.12, Frame Relay Fragmentation Implementation Agreement. 7. FRF.16, Multilink Frame Relay (MFR) PVC Implementation Agreement. HDLC Standards 1. International Organization for Standardization, ISO Standard 3309-1993, "Information Technology - Telecommunications and information exchange between systems - High-Level Data Link Control (HDLC) procedures - Frame structure", December 1993. 2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force, July 1994. Misc. References 1. PMC-981125 - "High Density T1/E1 Framer with Integrated VT/TU Mapper and M13 Multiplexer (TEMUX) Data Sheet", PMC-Sierra Inc.
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FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
4
APPLICATIONS IETF PPP interfaces for routers. Frame Relay interfaces for ATM or Frame Relay switches and multiplexers. FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexers. Internet/Intranet access equipment. Multiservice DSLAM equipment.
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FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
5
APPLICATION EXAMPLES Figure 1 - An OC-12 access card for a router
77 MHz Telecom Bus 77MHz SBI Bus Any-PHY Bus System Backplane
PM8316 TEMUX-84
Ingress/Egress Packet RAMS Context RAM
PM8316 TEMUX-84 PM5313 SPECTRA-622 PM8316 TEMUX-84
Backplane ASIC
PM7388 FREEDM-336A1024
Resequence RAMS PM8316 TEMUX-84
APEX-622
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
6
BLOCK DIAGRAM Figure 2 - The block diagram of FREEDM-336A1024
TCLK[11:0] TD[11:0] BCLK AD[31:0] ADSB CSB WR BURSTB BLAST READYB BTERMB WRDONEB INTHIB INTLOB BUSPOL
RSTB PMCTEST SCAN_EN DLLTEST
SYSCLK
TDO TDI TCK TMS TRSTB
DDLL-140
JTAG
Microprocessor I/F (BUMP2) Egress Queue Manager (EQM-12) Tx Fragment Builder (TFRAG)
AC1FP C1FPOUT
Tx ANY-PHY I/F (TAPI-12)
ADATA[7:0] ADP APL AV5 AJUST_REQ ADETECT[1:0] AACTIVE
Insert SBI (INSBI336)
Transmit Channel Assigner (TCAS-12)
Tx HDLC Processor/ Partial Packet Buffer (THDL-12)
TXCLK TXADDR[15:0] TPA TXDATA[15:0] TXPRTY TRDY TSX TEOP TMOD TERR
CCDAT[35:0] CCADD[17:0] CCWEB CCSELB
SRAMC (SRAMC)
CCBSELB
CBDAT[47:0] CBADD[12:0] CBWEB CBCSB CBRASB CBCASB CBBS[1:0]
REFCLK
Performance Monitor (PM-12)
CB DRAM Controller (CB_DRAMC)
DDATA[7:0] DDP DPL DV5
DC1FP
Extract SBI (EXSBI336)
Receive Channel Assigner (RCAS-12)
Rx HDLC Processor/ Partial Packet Buffer (RHDL-12)
Rx Fragment Builder (RFRAG)
Frame Builder (FRMBLD)
Ingress Queue Manager (IQM-12)
RS DRAM Controller (RS_DRAMC)
Rx ANY-PHY I/F (RAPI-12)
RCLK[11:0] RD[11:0]
RSDAT[31:0] RSADD[12:0] RSWEB RSCSB RSRASB RSCASB RSBS[1:0] DQM
RXCLK RXADDR[3:0] RPA RENB RXDATA[15:0] RXPRTY RVAL RSX RSOP REOP RMOD RERR
Data Control
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FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
7
DESCRIPTION The FREEDM-336A1024 device is a monolithic integrated circuit supporting highly channelized termination of HDLC-framed Point to Point Protocol (PPP) and Frame Relay, including multilink variants. On the Line side, the FREEDM-336A1024 device supports an SBI336 interface and twelve clock and data interfaces for subrate DS3/E3 support. The FREEDM336A1024 can support up to 1024 HDLC channels provisioned across these interfaces. On the system side, the FREEDM-336A1024 provides a Level 2 and Level 3 APPI presenting a channelized interface capable of supporting full frame/packet transfers as well as fragment data transfers. Rate adaptation between the line and system interfaces is provided by external buffers. The FREEDM-336A1024 terminates up to 1024 HDLC channels of HDLC framed PPP or Frame Relay with speeds ranging from 56 Kbps to 52 Mbps in the ingress direction. HDLC channels may contain a mix of protocols and speeds up to an aggregate of 622 Mbps. FREEDM-336A1024 provides HDLC header removal, CRC checking and stripping. Data path termination including frame/packet re-assembly and multilink termination is provided in hardware. The FREEDM-336A1024 receives packets from the external controller. The FREEDM-336A1024 provides support for ML-FR and ML-PPP protocols by fragmenting transmitted packets, appending the appropriate sequence number and assigning the fragment to an HDLC channel within the multilink bundle. FREEDM-336A1024 is also capable of supporting full packet transfer on up to 1024 HDLC channels that are not configured to support multlilink. The HDLC processor within FREEDM-336A1024 encapsulates the data with HDLC flags, CRC bytes and performs the appropriate bit stuffing.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
8
PIN DIAGRAM
The FREEDM-336A1024 is manufactured in a 520 pin (1.27 mil pitch) enhanced ball grid array package. (Bottom View)
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
9
PIN DESCRIPTION - SBI Interface signals (30 pins) Type Input Pin No. P30 Function The SBI reference clock signal (REFCLK) provides reference timing for the SBI ADD and DROP busses. REFCLK is nominally a 50% duty cycle clock of frequency 77.76 MHz 20ppm. DC1FP Input P31 The C1 octet frame pulse signal (DC1FP) for the drop bus provides frame synchronization for devices connected via an SBI interface. DC1FP must be asserted for 1 REFCLK cycle every 500 s or multiples thereof (i.e. every 38880 x n REFCLK cycles, where n is a positive integer). All devices interconnected via the SBI drop interface must be synchronized to a DC1FP signal from a single source. DC1FP is sampled on the rising edge of REFCLK. Note - If the SBI bus is being operated in synchronous mode, DC1FP must be asserted for 1 REFCLK cycle every 6 ms or multiples thereof.
Table 2
Pin Name REFCLK
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name AC1FP
Type Input
Pin No. K30
Function The C1 octet frame pulse signal (AC1FP) for the add bus provides frame synchronization for devices connected via an SBI interface. AC1FP must be asserted for 1 REFCLK cycle every 500 s or multiples thereof (i.e. every 38880 n REFCLK cycles, where n is a positive integer). All devices interconnected via the add SBI interface must be synchronized to an AC1FP signal from a single source. AC1FP is sampled on the rising edge of REFCLK. Note - If the SBI bus is being operated in synchronous mode, AC1FP must be asserted for 1 REFCLK cycle every 6 ms or multiples thereof.
C1FPOUT
Output
K31
The C1 octet frame pulse output signal (C1FPOUT) may be used to provide frame synchronization for devices interconnected via an SBI interface. C1FPOUT is asserted for 1 REFCLK cycle every 500 s (i.e. every 38880 REFCLK cycles). C1FPOUT is updated on the rising edge of REFCLK. Note - The C1FPOUT pulse is not suitable for use in systems in which the SBI bus is operated in synchronous mode.
DDATA[0] DDATA[1] DDATA[2] DDATA[3] DDATA[4] DDATA[5] DDATA[6] DDATA[7]
Input
R27 R28 R29 R30 R31 U31 U30 U27
The SBI DROP bus data signals (DDATA[7:0]) contain the time division multiplexed receive data from the up to 336 independently timed links. Data from each link is transported as a tributary within the SBI TDM bus structure. Multiple PHY devices can drive the SBI DROP bus at uniquely assigned tributary column positions. DDATA[7:0] are sampled on the rising edge of REFCLK.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name DDP
Type Input
Pin No. V31
Function The SBI DROP bus parity signal (DDP) carries the even or odd parity for the DROP bus signals. The parity calculation encompasses the DDATA[7:0], DPL and DV5 signals. Multiple PHY devices can drive DDP at uniquely assigned tributary column positions. This parity signal is intended to detect accidental PHY source clashes in the column assignment. DDP is sampled on the rising edge of REFCLK.
DPL
Input
V30
The SBI DROP bus payload signal (DPL) indicates valid data within the SBI TDM bus structure. This signal is asserted during all octets making up a tributary. This signal may be asserted during the V3 or H3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed TDM bus structure. This signal may be de-asserted during the octet following the V3 or H3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed TDM bus structure. Multiple PHY devices can drive DPL at uniquely assigned tributary column positions. DPL is sampled on the rising edge of REFCLK.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name DV5
Type Input
Pin No. V29
Function The SBI DROP bus payload indicator signal (DV5) locates the position of the floating payloads for each tributary within the SBI TDM bus structure. Timing differences between the port timing and the TDM bus timing are indicated by adjustments of this payload indicator relative to the fixed TDM bus structure. Multiple PHY devices can drive DV5 at uniquely assigned tributary column positions. All movements indicated by this signal must be accompanied by appropriate adjustments in the DPL signal. DV5 is sampled on the rising edge of REFCLK.
ADATA[0] ADATA[1] ADATA[2] ADATA[3] ADATA[4] ADATA[5] ADATA[6] ADATA[7]
Tristate Output
L28 L29 L30 M27 M28 M29 M30 M31
The SBI ADD bus data signals (ADATA[7:0]) contain the time division multiplexed transmit data from the up to 336 independently timed links. Data from each link is transported as a tributary within the SBI TDM bus structure. Multiple link layer devices can drive the SBI ADD bus at uniquely assigned tributary column positions. When the FREEDM336A1024 is not outputting data on a particular tributary column the ADATA[7:0] are driven or tri-stated based on the DEFAULT_DRV register value. ADATA[7:0] are updated on the rising edge of REFCLK.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name ADP
Type Tristate Output
Pin No. N27
Function The SBI ADD bus parity signal (ADP) carries the even or odd parity for the ADD bus signals. The parity calculation encompasses the ADATA[7:0], APL and AV5 signals. Multiple link layer devices can drive this signal at uniquely assigned tributary column positions. When the FREEDM-336A1024 is not outputting data on a particular tributary column ADP is driven or tri-stated based on the DEFAULT_DRV register value. This parity signal is intended to detect accidental link layer source clashes in the column assignment. ADP is updated on the rising edge of REFCLK.
APL
Tristate Output
N28
The SBI ADD bus payload signal (APL) indicates valid data within the SBI TDM bus structure. This signal is asserted during all octets making up a tributary. This signal may be asserted during the V3 or H3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed TDM bus structure. This signal may be de-asserted during the octet following the V3 or H3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed TDM bus structure. Multiple link layer devices can drive this signal at uniquely assigned tributary column positions. When the FREEDM-336A1024 is not outputting data on a particular tributary column APL is driven or tri-stated based on the DEFAULT_DRV register value. APL is updated on the rising edge of REFCLK.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name AV5
Type Tristate output
Pin No. N30
Function The SBI ADD bus payload indicator signal (AV5) locates the position of the floating payloads for each tributary within the SBI TDM bus structure. Timing differences between the port timing and the TDM bus timing are indicated by adjustments of this payload indicator relative to the fixed TDM bus structure. Multiple link layer devices can drive this signal at uniquely assigned tributary column positions. When the FREEDM-336A1024 is not outputting data on a particular tributary column AV5 is driven or tri-stated based on the DEFAULT_DRV register value. AV5 is updated on the rising edge of REFCLK.
ADETECT[0] ADETECT[1]
Input
P28 P29
The SBI ADD bus conflict detection signals (ADETECT[1:0]) may be connected to the AACTIVE outputs of other link layer devices sharing the SBI ADD bus. FREEDM336A1024 will tristate the SBI ADD bus signals ADATA[7:0], ADP, APL and AV5 if either of ADETECT[1] and ADETECT[0] is asserted. ADETECT[1:0] are asynchronous inputs.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name AJUST_REQ
Type Input
Pin No. N31
Function The SBI ADD bus justification request signal (AJUST_REQ) is used to speed up or slow down the output data rate of the FREEDM336A1024. Negative timing adjustments are requested by asserting AJUST_REQ during the V3 or H3 octet of the drop bus depending on the tributary type. In response to this the FREEDM-336A1024 will send an extra byte in the V3 or H3 octet of the next frame on the add bus along with a valid APL indicating a negative justification. Positive timing adjustments are requested by asserting AJUST_REQ during the octet following the V3 or H3 octet of the drop bus, depending on the tributary type. FREEDM336A1024 will respond to this by not sending an octet during the octet following the V3 or H3 octet of the next frame on the add bus and de-asserting APL to indicate a positive justification. AJUST_REQ is sampled on the rising edge of REFCLK.
AACTIVE
Output
P27
The SBI ADD bus active indicator signal (AACTIVE) is asserted whenever FREEDM336A1024 is driving the SBI ADD bus signals, ADATA[7:0], ADP, APL and AV5. All other Link Layer devices driving the SBI ADD bus should monitor this signal (to detect multiple sources accidentally driving the bus) and should cease driving the bus whenever a conflict is detected. AACTIVE is updated on the rising edge of REFCLK.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Table 3
- Clock/Data Interface signals (48 pins) Pin Name RCLK[0] RCLK [1] RCLK [2] RCLK [3] RCLK [4] RCLK [5] RCLK [6] RCLK [7] RCLK [8] RCLK [9] RCLK [10] RCLK [11] RD[0] RD[1] RD[2] RD[3] RD[4] RD[5] RD[6] RD[7] RD[8] RD[9] RD[10] RD[11] TCLK[0] TCLK [1] TCLK [2] TCLK [3] TCLK [4] TCLK [5] TCLK [6] TCLK [7] TCLK [8] TCLK [9] TCLK [10] TCLK [11] Type Input Pin No. AJ25 AL25 AJ24 AG23 AH23 AL23 AJ22 AL22 AJ21 AG20 AJ20 AL20 AK25 AH24 AK24 AL24 AJ23 AH22 AK22 AH21 AK21 AH20 AK20 AG19 B13 A13 E14 D14 C14 B14 A14 E15 D15 C15 B15 A15 Function The receive line clock signals (RCLK[11:0]) contain the recovered line clock for the 12 independently timed links. RCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e. not part of the HDLC packet). RCLK[11:0] is nominally a 50% duty cycle clock between 0 and 52 MHz. The RCLK[n] inputs are invalid and should be tied low when their associated link is not configured for operation. The receive data signals (RD[11:0]) contain the recovered line data for the 12 independently timed links. RD[11:0] contain HDLC packet data. For certain transmission formats, RD[11:0] may contain placeholder bits or time-slots. RCLK[n] must be externally gapped during the place holder positions in the RD[n] stream. The FREEDM-336A1024 supports a maximum data rate of 52 Mbps on each link. RD[11:0] is sampled on the rising edge of the corresponding RCLK[11:0]. The transmit line clock signals (TCLK[11:0]) contain the transmit clocks for the 12 independently timed links. TCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e. not part of the HDLC packet). TCLK[11:0] is nominally a 50% duty cycle clock between 0 and 52 MHz. The TCLK[n] inputs are invalid and should be tied low when their associated link is not configured for operation
Input
Input
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name TD[0] TD[1] TD[2] TD[3] TD[4] TD[5] TD[6] TD[7] TD[8] TD[9] TD[10] TD[11]
Type Output
Pin No. A17 B17 E17 A18 B18 C18 D18 E18 A19 B19 C19 E19
Function The transmit data signals (TD[11:0]) contain the transmit data for the 12 independently timed links. TD[11:0] contains HDLC packet data. For certain transmission formats, TD[11:0] may contain placeholder bits or time-slots. TCLK[n] must be externally gapped during the place holder positions in the TD[n] stream. The FREEDM-336A1024 supports a maximum data rate of 52 Mbps on each link. In normal operation, TD[11:0] is updated on the falling edge of the corresponding TCLK[11:0] clock. In loopback mode, TD[11:0] are updated on the falling edge of the corresponding RCLK[11:0] clock.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Table 4
- ANY-PHY Packet Interface signals (70 pins)
Note: ANY-PHY Level is s/w programmable. Pin Name TXCLK Type Input Pin No. Y3 Function The transmit clock signal (TXCLK) provides timing for the transmit ANY-PHY packet interface. ANY-PHY Level 2 Mode: TXCLK is a nominally 50% duty cycle, 25 to 52 MHz clock. ANY-PHY Level 3 Mode: TXCLK is a nominally 50% duty cycle, 50 to 104 MHz clock TXADDR[0] Input TXADDR[1] TXADDR[2] TXADDR[3] TXADDR[4] TXADDR[5] TXADDR[6] TXADDR[7] TXADDR[8] TXADDR[9] TXADDR[10] TXADDR[11] TXADDR[12] TXADDR[13] TXADDR[14] TXADDR[15] V5 V4 V3 V2 V1 U5 U4 U3 U2 U1 R1 R2 R5 P1 P2 P3 The transmit address signals (TXADDR[15:0]) provide a channel address for polling a transmit ANY-PHY channel FIFO. The FREEDM-336A1024 compares the TXADDR[15:0] to the base and range registers to determine if the ANY-PHY channel being polled resides within the FREEDM-336A1024. An ANY-PHY channel with an address that is greater than or equal to the base register and less than or equal to the maximum address as defined by the range plus channel base address resides within the FREEDM-336A1024. The TXADDR[15:0] signals are sampled on the rising edge of TXCLK.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name TPA
Type Tristate Output
Pin No. P4
Function The transmit packet available (TPA) signal reflects the status of a poll of a transmit ANYPHY channel FIFO. TPA returns the polled results for ANY-PHY channel address `n' provided on TXADDR[15:0]. TPA is coded as follows: TPA = "1" => Space to accept a 9600 byte packet. TPA = "0" => No Space to accept a 9600 byte packet.It is the responsibility of the external controller to prevent ANY-PHY channel underflow or overflow conditions by adequately polling each channel before data transfer. TPA is updated on the rising edge of TXCLK. TPA is tristate during reset. Once a packet has started to be transferred, TPA will reflect the ability to accept another complete packet. ANY-PHY Level 2 Mode: TPA is tristate when an ANY-PHY channel address other than ANY-PHY channels residing in the FREEDM is provided on TXADDR[15:0]. An ANY-PHY channel with an address that is less than the channel base address register or outside the range address register within the FREEDM336A1024 is identified as an ANY-PHY channel that does not reside within the FREEDM-336A1024. TPA = Z for unprovisioned channels. It is recommended that TPA be connected externally to a weak pull-down, e.g. 470W.
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FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name cont'd
Type
Pin No.
Function ANY-PHY Level 3 Mode: TPA returns the value "0" when an ANY-PHY channel address other than ANY-PHY channels residing in the FREEDM is provided on TXADDR[15:0]. The TPA poll response is invalid if it corresponds to a TXADDR poll coincident with the start of a segment transfer (ie on the cycle in which TSX is driven high). TPA=0 for unprovisioned channels.
TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXDATA[8] TXDATA[9] TXDATA[10] TXDATA[11] TXDATA[12] TXDATA[13] TXDATA[14] TXDATA[15]
Input
P5 N1 N2 N3 N5 M1 M2 M3 M4 M5 L2 L3 L4 K1 K2 K3
ANY-PHY Level 2 Mode The transmit data signals (TXDATA[15:0]) contain the transmit ANY-PHY packet interface (APPI) data provided by the external controller. Data must be presented in big endian order, i.e. the byte in TXDATA[15:8] is transmitted by the FREEDM-336A1024 before the byte in TXDATA[7:0]. The first word of each data transfer contains an address to identify the device and ANYPHY channel associated with the data being transferred. This prepended address must be qualified with the TSX signal. The FREEDM336A1024 compares the first two bytes to the base and range registers to determine if the ANY-PHY channel resides within the FREEDM-336A1024.The FREEDM336A1024 will not respond to ANY-PHY channel addresses outside the high and low address registers stored in the TAPI-12 base and range address registers. The second and any subsequent words of each data transfer contain packet data. The TXDATA[15:0] signals are sampled on the rising edge of TXCLK.
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FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name Cont'd
Type
Pin No.
Function ANY-PHY Level 3 Mode: The transmit data signals (TXDATA[7:0]) contain the transmit ANY-PHY packet interface (APPI) data provided by the external controller. The first two bytes of each data transfer contains an address to identify the device and ANY-PHY channel associated with the data being transferred. The first byte of this prepended address must be qualified with the TSX signal. The FREEDM-336A1024 compares the first two bytes to the TAPI-12 base and range registers to determine if the ANY-PHY channel resides within the FREEDM-336A1024.The FREEDM336A1024 will not respond to ANY-PHY channel addresses outside the base and range registers. The third and any subsequent bytes of each data transfer contain packet data. The TXDATA[7:0] signals are sampled on the rising edge of TXCLK. TXDATA[15:8] are not used by FREEDM336A1024 when operating in ANY-PHY Level 3 mode and should be tied low.
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FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name TXPRTY
Type Input
Pin No. K4
Function ANY-PHY Level 2 Mode: The transmit parity signal (TXPRTY) reflects the odd parity calculated over the TXDATA[15:0] signals (regardless of TMOD state). TXPRTY is only valid when TXDATA[15:0] are valid. ANY-PHY Level 3 Mode: The transmit parity signal (TXPRTY) reflects the odd parity calculated over the TXDATA[7:0] signals. TXPRTY is only valid when TXDATA[7:0] are valid. Regardless of mode of operation TXPRTY is sampled on the rising edge of TXCLK.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name TRDY
Type Tristate Output
Pin No. J1
Function The transmit ready signal (TRDY) indicates the ability of the transmit ANY-PHY packet interface (APPI) to accept data. When TRDY is set low, the transmit APPI is unable to accept further data. When TRDY is set high, data provided on the transmit APPI will be accepted by the FREEDM-336A1024 device If TRDY is driven low, the external controller must hold the data on TXDATA until TRDY is driven high and then tri-state. TRDY may be driven low for 0 or more TXCLK cycles before it is driven high. TRDY is considered valid from two cycles after the start of transfer until the cycle in which it is asserted high (it can only backpressure once at the start of transfer). A new transfer can not be initiated earlier than one clock after TRDY is sampled high. TRDY is tristate during reset. TRDY is updated on the rising edge of TXCLK. ANY-PHY Level 2 Mode TRDY is valid one TXCLK cycle after TSX is sampled high. TRDY is asserted by the FREEDM-336A1024 device, which was selected by the in-band ANY-PHY channel address on TXDATA[15:0]. TRDY will only be driven high for one clock cycle, it is always driven tristate one TXCLK cycle after it is driven high. It is recommended that TRDY be connected externally to a weak pull-up, e.g. 10 kW. ANY-PHY Level 3 Mode TRDY is valid one TXCLK cycle after TSX is sampled high and remains valid up to and including the cycle in which it is driven high.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name TSX
Type Input
Pin No. K5
Function The transmit start of transfer signal (TSX) denotes the start of data transfer on the transmit APPI. The TSX signal is sampled on the rising edge of TXCLK. ANY-PHY Level 2 Mode When the TSX signal is sampled high, the sampled word on the TXDATA[15:0] signals contain the ANY-PHY channel address associated with the data to follow. When the TSX signal is sampled low, the sampled word on the TXDATA[15:0] signals do not contain an ANY-PHY channel address. ANY-PHY Level 3 Mode: When the TSX signal is sampled high, the sampled byte on the TXDATA[7:0] signals contain the most significant byte of the ANYPHY channel address associated with the data to follow. When the TSX signal is sampled low, the sampled word on the TXDATA[7:0] signals do not contain the first byte of the ANY-PHY channel address.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name TEOP
Type Input
Pin No. J2
Function The transmit end of packet signal (TEOP) denotes the end of a packet. TEOP is only valid during data transfer TEOP is sampled on the rising edge of TXCLK ANY-PHY Level 2 Mode When TEOP is sampled high, the data on TXDATA[15:0] is the last word of a packet (fragment). When TEOP is sampled low, the data on TXDATA[15:0] is not the last word of a packet (fragment). ANY-PHY Level 3 Mode: When TEOP is sampled high, the data on TXDATA[7:0] is the last byte of a packet (fragment). When TEOP is sampled low, the data on TXDATA[7:0] is not the last byte of a packet (fragment).
TMOD
Input
J3
ANY-PHY Level 2 Mode The transmit word modulo signal (TMOD) indicates the size of the current word on TXDATA[15:0]. TMOD is only valid when TEOP is sampled high. When TMOD is sampled high and TEOP is sampled high, only the TXDATA[15:8] signals contain valid data and the TXDATA[7:0] signals are invalid. When TMOD is sampled low and TEOP is sampled high, the complete word on TXDATA[15:0] contains valid data. TMOD must be set low when TEOP is set low. TMOD is sampled on the rising edge of TXCLK. ANY-PHY Level 3 Mode: TMOD is not used. The last valid byte of data on TXDATA[7:0] is sampled when TEOP is sampled high
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name TERR
Type Input
Pin No. J4
Function The transmit error signal (TERR) indicates that the current packet is erred and should be aborted. TERR is only valid when TEOP is sampled high. When TERR is sampled high and TEOP is sampled high, the current packet is erred and the FREEDM-336A1024 will respond accordingly. When TERR is sampled low and TEOP is sampled high, the current packet is not erred. TERR must be set low when TEOP is set low. TERR is sampled on the rising edge of TXCLK.
RXCLK
Input
AE5
The receive clock signal (RXCLK) provides timing for the receive ANY-PHY packet interface (APPI). ANY-PHY Level 2 Mode RXCLK is a nominally 50% duty cycle, 25 to 52 MHz clock ANY-PHY Level 3 Mode: RXCLK is a nominally 50% duty cycle, 50 to 104 MHz clock.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RXADDR[0] RXADDR[1] RXADDR[2] RXADDR[3]
Type Input
Pin No. AF2 AE4 AE3 AE2
Function ANY-PHY Level 2 Mode: The receive address signals (RXADDR[3:0]) serve two functions - device polling and device selection. When polling, the RXADDR[3:0] signals provide an address for polling a FREEDM-336A1024 device for receive data available in any one of its 1024 ANY-PHY channels. Polling results are returned on the RPA tristate output. During selection, the address on the RXADDR[3:0] signals is qualified with the RENB signal to select a FREEDM-336A1024 device enabling it to output data on the receive APPI. Note that up to fifteen FREEDM-336A1024 devices may share a single external controller (one address is reserved as a null address). The Rx APPI of each FREEDM336A1024 device is identified by the device base address in the RAPI-12 Base Address register. The RXADDR[3:0] signals are sampled on the rising edge of RXCLK. ANY-PHY Level 3 Mode: RXADDR is not used as the interface is point-to-point.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RPA
Type Tristate Output
Pin No. AE1
Function The receive packet/fragment available signal (RPA) reflects the status of a poll on the receive APPI of a FREEDM-336A1024 device RPA is tristate during reset and when a device address other than the FREEDM336A1024's device base address is provided on RXADDR[3:0]. An FREEDM-336A1024 device must not be selected for receive data transfer unless it has been polled and responded that it has data ready to transfer. When the RXADDR[3:0] inputs match the device base address in the RAPI-12 Base Address register, that FREEDM-336A1024 device drives RPA one RXCLK cycle after sampling RXADDR[3:0]. RPA is updated on the rising edge of RXCLK. ANY-PHY Level 2 Packet Mode: When RPA is set high, the polled FREEDM336A1024 still has sufficient data to undertake another ANY-PHY transfer. When RPA is set low, the polled FREEDM336A1024 device does not have data ready to transfer ANY-PHY Level 3 Mode: RPA is not used and is tri-stated.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RENB
Type Input
Pin No. AD4
Function The receive enable signal (RENB) is used to throttle the FREEDM-336A1024. RENB is sampled on the rising edge of RXCLK. To commence data transfer, RENB must be sampled low. ANY-PHY Level 2 Mode: The receive enable signal (RENB) qualifies the RXADDR[3:0] signals for selection of a FREEDM-336A1024 device. When RENB is sampled high and then low in consecutive RXCLK cycles, the address on RXADDR[3:0] during the cycle when RENB is sampled high selects a FREEDM-336A1024 device enabling it to output data on the receive APPI. The Rx APPI of each FREEDM336A1024 device is identified by the device base address in the RAPI-12 Base Address register. RENB may also be used to throttle the FREEDM-336A1024 during data transfer on the Rx APPI. When the FREEDM-336A1024 samples RENB high during data transfer, the FREEDM-336A1024 will pause the data transfer and tri-state the receive APPI outputs (except RPA) until RENB is returned low. Since the ANY-PHY bus specification does not support deselecting during data transfers, the address on the RXADDR[3:0] inputs during the cycle before RENB is returned low must either re-select the same FREEDM-336A1024 device or be a null address. The polling function of the RXADDR[3:0] and RPA signals operates regardless of the state of RENB.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name Cont'd
Type
Pin No.
Function It is the responsibility of the external controller to prevent overflow by providing each FREEDM-336A1024 device on an ANYPHY point to multi-point bus sufficient bandwidth through selection. ANY-PHY Level 3 Mode: RENB is used to throttle the FREEDM336A1024 during data transfer on Rx APPI. When the FREEDM-336A1024 samples RENB high during data transfer, the FREEDM-336A1024 will pause the data transfer until RENB is returned low.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXDATA[8] RXDATA[9] RXDATA[10] RXDATA[11] RXDATA[12] RXDATA[13] RXDATA[14] RXDATA[15]
Type Tristate Output
Pin No. AD3 AD2 AC5 AD1 AC4 AC2 AB5 AC1 AB4 AB3 AB2 AB1 AA4 AA3 AA2 Y5
Function ANY-PHY Level 2 Mode The receive data signals (RXDATA[15:0]) contain the receive ANY-PHY packet interface (APPI) data output by the FREEDM-336A1024 when selected. Data is presented in big endian format; i.e. the byte in RXDATA[15:8] was received by the FREEDM-336A1024 before the byte in RXDATA[7:0]. The first word of each data transfer (when RSX is high) contains an address to identify the device and ANY-PHY channel associated with the data being transferred. The second and any subsequent words of each data transfer contain valid data. The FREEDM336A1024 may be programmed to overwrite RXDATA[7:0] of the final word of each packet transfer (REOP is high) with the status of packet reception when that packet is erred (RERR is high). This status information is encoded as follows: RXDATA[7:0] Error 01H 02H 04H 08H 10H 81H 82H 84H 88H 90H Fragments Channel FIFO Overrun Packet Length violation FCS Error Non-Octet Aligned HDLC Packet Abort Unexpected Presence of SN Unsupported Header Format Lost Datagram Unexpected SN Excessive Number of
Note1 : Excessive Number of Fragments only applies when the output format is frame/packet out (not fragment out).
The RXDATA[15:0] signals are tristated when the FREEDM-336A1024 device is not selected via the RENB signal.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name Cont'd
Type
Pin No.
Function The RXDATA[15:0] signals are updated on the rising edge of RXCLK. ANY-PHY Level 3 Mode: The receive data signals (RXDATA[7:0]) contain the receive ANY-PHY packet interface (APPI) data output by the FREEDM-336A1024 when selected. The first and second bytes of each data transfer contains an address to identify the device and channel associated with the data being transferred. The third and any subsequent bytes of each data transfer contain valid data. The FREEDM-336A1024 may be programmed to overwrite RXDATA[7:0] of the final word of each packet transfer (REOP is high) with the status of packet reception when that packet is erred (RERR is high). This status information is encoded as for the ANY-PHY Level 2 Mode (above). The RXDATA[15:8] signals are tristated when the FREEDM-336A1024 device operating in 8 bit mode. The RXDATA[7:0] signals are driven but not considered valid when the RENB signal is high. The RXDATA[7:0] signals are updated on the rising edge of RXCLK.
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38
PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RXPRTY
Type Tristate Output
Pin No. Y4
Function ANY-PHY Level 2 Mode The receive parity signal (RXPRTY) reflects the odd parity calculated over the RXDATA[15:0] signals (regardless of RMOD state). RXPRTY is driven/tristated at the same time as RXDATA[15:0]. ANY-PHY Level 3 Mode: The receive parity signal (RXPRTY) reflects the odd parity calculated over the RXDATA[7:0] signals. RXPRTY is valid when RXDATA[7:0] is valid. Regardless of mode, RXPRTY is updated on the rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE
39
PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RSX
Type Tristate Output
Pin No. Y2
Function The receive start of transfer signal (RSX) denotes the start of data transfer on the receive APPI. RSX is updated on the rising edge of RXCLK. ANY-PHY Level 2 Mode When the RSX signal is set high, the data on the RXDATA[15:0] signals contains the address that identifies the device and channel associated with the data to follow. When the RSX signal is sampled low, the word on the RXDATA[15:0] signals does not contain a channel address. RSX is tristated when the FREEDM336A1024 device is not selected via the RENB signal. RSX is updated on the rising edge of RXCLK. It is recommended that RSX be connected externally to a weak pull-down, e.g. 10 kW. ANY-PHY Level 3 Mode When the RSX signal is set high, the data on the RXDATA[7:0] signals contains the most significant byte of the address that identifies the device and channel associated with the data to follow. When the RSX signal is sampled low, the byte on the RXDATA[7:0] signals does not contain the first byte of the channel address.
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40
PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RSOP
Type Tristate Output
Pin No. Y1
Function Receive Start of Packet. Marks the cycle containing the start of the packet. The FREEDM-336A1024 drives RSOP high at the start of a packet in a transfer period and holds RSOP low afterwards. RSOP is used when supporting both ANY-PHY Level 2 and 3 operating modes. ANY-PHY Level 2 Mode: RSOP is driven high one clock cycle after the RSX is driven high. RSOP is tri-stated after the last word of the packet is sent. ANY-PHY Level 3 Mode: RSOP is driven high two clock cycles after the RSX is driven high. RSOP is tri-stated after the last byte of the packet is sent.
REOP
Tristate Output
W5
The receive end of packet signal (REOP) denotes the end of a packet. REOP is only valid during data transfer. REOP is updated on the rising edge of RXCLK. ANY-PHY Level 2 Mode: When REOP is set high, RXDATA[15:0] contains the last data byte of a packet. When REOP is set low, RXDATA[15:0] does not contain the last data byte of a packet. REOP is tristated when the FREEDM336A1024 device is not selected via the RENB signal. ANY-PHY Level 3 Mode: When REOP is set high, RXDATA[7:0] contains the last data byte of a packet. When REOP is set low, RXDATA[7:0] does not contain the last data byte of a packet.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE
41
PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RMOD
Type Tristate Output
Pin No. W4
Function ANY-PHY Level 2 Mode: The receive word modulo signal (RMOD) indicates the size of the current word on RXDATA[15:0]. When RXDATA[15:0] does not contain the last byte of a packet (REOP set low), RMOD is set low. When RMOD is set high and REOP is set high, RXDATA[15:8] contains the last data byte of a packet. When RMOD is set low and REOP is set high, RXDATA[7:0] contains the last byte of the packet, or optionally, the error status byte. The behavior of RMOD relates only to packet data and is unaffected when the FREEDM-336A1024 device is programmed to overwrite RXDATA[7:0] with status information when erred packets are received. RMOD is tristated when the FREEDM336A1024 device is not selected via the RENB signal. RMOD is updated on the rising edge of RXCLK. ANY-PHY Level 3 Mode: RMOD is not used. The last valid byte of data on RXDATA[7:0] is sampled when REOP is sampled high. RMOD is tristated when the FREEDM336A1024 is operating in ANY-PHY level 3 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE
42
PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RERR
Type Tristate Output
Pin No. W1
Function The receive error signal (RERR) indicates that the current packet is erred and should be discarded RERR is tristated when the FREEDM336A1024 device is not selected via the RENB signal. RERR is updated on the rising edge of RXCLK. The receive error signal (RERR) indicates that the current packet is erred and should be discarded. When RXDATA[15:0] (ANY-PHY Level 2 mode) or RXDATA[7:0] (ANY-PHY Level 3 mode) does not contain the last byte of a packet (REOP set low), RERR is set low. When RERR is set high and REOP is set high, the current packet is erred. When RERR is set low and REOP is set high, the current packet is not erred. The FREEDM-336A1024 may be programmed to overwrite RXDATA[7:0] of the final word of each packet transfer (REOP set high) with the status of packet reception when that packet is erred (RERR is high). ANY-PHY Level 2 Mode: RERR is tristated when the FREEDM336A1024 device is not selected via the RENB signal. ANY-PHY Level 3 Mode: RERR is driven low when the FREEDM336A1024 device is not selected via the RENB signal.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE
43
PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Pin Name RVAL
Type Tristate Output
Pin No. W2
Function The receive data valid (RVAL) is asserted when packet data is being output on RXDATA. It is de-asserted whenever the FREEDM-336A1024 device is selected, but not outputting packet data on RXDATA[15:0]. (E.g., when RSX is high and address prepend is being output on RXDATA, RVAL is de-asserted.) RVAL is updated on the rising edge of RXCLK. ANY-PHY Level 2 Mode: RVAL is tristated when the FREEDM336A1024 device is not selected via the RENB signal. ANY-PHY Level 3 Mode: RVAL is driven low when the FREEDM336A1024 device is not selected via the RENB signal.
Table 5
- Re-Sequencing SDRAM Interface (52 Signals) Type Output Pin No. AB31 Function Re-Sequencing SDRAM Chip Select Bar. RSCSB, RSRASB, RSCASB, and RSWEB define the command being sent to the SDRAM. RSCSB is updated on the rising edge of SYSCLK.
Pin Name RSCSB
RSRASB
Output
AB30
Re-Sequencing SDRAM Row Address Strobe Bar. RSCSB, RSRASB, RSCASB, and RSWEB define the command being sent to the SDRAM. RSRASB is updated on the rising edge of SYSCLK.
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
RSCASB
Output
AB29
Re-Sequencing SDRAM Column Address Strobe Bar. RSCSB, RSRASB, RSCASB, and RSWEB define the command being sent to the SDRAM. RSCASB is updated on the rising edge of SYSCLK.
RSWEB
Output
AA28
Re-Sequencing SDRAM Write Enable Bar. RSCSB, RSRASB, RSCASB, and RSWEB define the command being sent to the SDRAM. RSWEB is updated on the rising edge of SYSCLK.
RSADD[0] RSADD[1] RSADD[2] RSADD[3] RSADD[4] RSADD[5] RSADD[6] RSADD[7] RSADD[8] RSADD[9] RSADD[10] RSADD[11] RSADD[12] RSBS[0] RSBS[1]
Output
V28 V27 W31 W30 W29 W27 Y31 Y30 Y29 Y28 Y27 AA30 AA29 AB28 AC31
Re-Sequencing SDRAM Address. The ReSequencing SDRAM address outputs identify the row address (RSADD[12:0]) and column address (RSADD[7:0]) for the locations accessed. RSADD[12:0] is updated on the rising edge of SYSCLK.
Output
Re-Sequencing SDRAM Bank Select. The bank select signal determines which bank of a dual/quad bank Re-Sequencing SDRAM chip is active. RSBS[1:0] is generated along with the row address when RSRASB is asserted low. RSBS is updated on the rising edge of SYSCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
RSDAT[0] RSDAT[1] RSDAT[2] RSDAT[3] RSDAT[4] RSDAT[5] RSDAT[6] RSDAT[7] RSDAT[8] RSDAT[9] RSDAT[10] RSDAT[11] RSDAT[12] RSDAT[13] RSDAT[14] RSDAT[15] RSDAT[16] RSDAT[17] RSDAT[18] RSDAT[19] RSDAT[20] RSDAT[21] RSDAT[22] RSDAT[23] RSDAT[24] RSDAT[25] RSDAT[26] RSDAT[27] RSDAT[28] RSDAT[29] RSDAT[30] RSDAT[31] DQM
I/O
AB27 AC30 AC29 AC28 AD31 AC27 AD28 AE31 AD27 AE29 AE28 AF30 AE27 AF29 AG31 AF28 AG30 AF27 AG29 AH30 AG28 AH27 AK28 AJ27 AG26 AK27 AH26 AL27 AJ26 AG25 AK26 AH25 AC3
Re-Sequencing SDRAM Data. The bidirectional Re-Sequencing SDRAM data bus pins interface directly with the ReSequencing SDRAM data ports. RSDAT[31:0] is updated/tristated on the rising edge of SYSCLK.
Output
Drives DQMH and DQML inputs of all SDRAMs. During the SDRAM initialization sequence this signal is set "high". Otherwise it is "low" at all times as the DRAM Controllers do not utilize the "masking" functionality of the memories. DQM is updated on the rising edge of SYSCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS INTERNAL USE
46
PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
Table 6
- Context Memory Synchronous SSRAM Interface (57 Signals) Type I/O Pin No. A20 B20 C20 D20 E20 B21 C21 D21 A22 B22 C22 D22 A23 E22 B23 C23 D23 A24 E23 D24 A25 E24 C25 D25 B26 E25 C26 A27 D26 B27 E26 C27 B28 D27 E28 D30 Function Context Memory SSRAM Data. The bidirectional SSRAM data bus pins interface directly with the synchronous SSRAM data ports. The FREEDM-336A1024 presents valid data on the CCDAT[35:0] pins upon the rising edge of SYSCLK during write cycles. CCDAT [35:0] is tristated on the rising edge of SYSCLK for read cycles. CCDAT [35:0] is sampled/updated/tristated on the rising edge of SYSCLK.
Pin Name CCDAT[0] CCDAT[1] CCDAT[2] CCDAT[3] CCDAT[4] CCDAT[5] CCDAT[6] CCDAT[7] CCDAT[8] CCDAT[9] CCDAT[10] CCDAT[11] CCDAT[12] CCDAT[13] CCDAT[14] CCDAT[15] CCDAT[16] CCDAT[17] CCDAT[18] CCDAT[19] CCDAT[20] CCDAT[21] CCDAT[22] CCDAT[23] CCDAT[24] CCDAT[25] CCDAT[26] CCDAT[27] CCDAT[28] CCDAT[29] CCDAT[30] CCDAT[31] CCDAT[32] CCDAT[33] CCDAT[34] CCDAT[35]
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PRELIMINARY DATASHEET PMC-1991476 ISSUE 7
FREEDMTM-336A1024
FRAME ENGINE AND DATA LINK MANAGER 336A1024
CCADD[0] CCADD[1] CCADD[2] CCADD[3] CCADD[4] CCADD[5] CCADD[6] CCADD[7] CCADD[8] CCADD[9] CCADD[10] CCADD[11] CCADD[12] CCADD[13] CCADD[14] CCADD[15] CCADD[16] CCADD[17] CCWEB
Output
J31 K27 J28 H31 J27 H30 H29 H28 G31 G30 G29 G28 F30 G27 F29 E31 F28 E30 F27
Context Memory SSRAM Address. The SSRAM address outputs identify the SSRAM locations accessed. CCADD[17:0] is updated on the rising edge of SYSCLK.
Output
Context Memory SSRAM Write Bar. CCWEB determines the cycle type when CCSELB is asserted low. When CCWEB is asserted high, the cycle type is a read. When CCWEB is asserted low, the cycle type is a write. CCWEB is updated on the rising edge of SYSCLK.
CCSELB
Output
E29
Context Memory SSRAM Chip Enable Bar. CCSELB initiates an access. When CCSELB is asserted low, the external SSRAM samples the address and CCWEB asserted by the FREEDM-336A1024. CCSELB is updated on the rising edge of SYSCLK.
CCBSELB
Output
K29
SSRAM Bank Select This active low output is provided to enable glueless connection to 4 banks of Standard/ZBT SSRAM: * CCBSEL is the inverse of CCADD[16]. CCBSEL and CCADD[16:17] are used to select 4 banks when 64x36 devices are used.
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Table 7
- Chunk Buffer SDRAM Interface (67 Signals) Type Output Pin No. AF5 Function Chunk Buffer SDRAM Chip Select Bar. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. CBCSB is updated on the rising edge of SYSCLK.
Pin Name CBCSB
CBRASB
Output
AG2
Chunk Buffer SDRAM Row Address Strobe Bar. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. CBRASB is updated on the rising edge of SYSCLK.
CBCASB
Output
AF4
Chunk Buffer SDRAM Column Address Strobe Bar. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. CBCASB is updated on the rising edge of SYSCLK.
CBWEB
Output
AG3
Chunk Buffer SDRAM Write Enable Bar. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. CBWEB is updated on the rising edge of SYSCLK.
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CBADD[0] CBADD[1] CBADD[2] CBADD[3] CBADD[4] CBADD[5] CBADD[6] CBADD[7] CBADD[8] CBADD[9] CBADD[10] CBADD[11] CBADD[12] CBBS[0] CBBS[1]
Output
AH7 AK6 AG7 AJ6 AL5 AH6 AK5 AG6 AJ5 AK4 AH5 AG4 AH2 AG1 AF3
Chunk Buffer SDRAM Address. The Chunk Buffer SDRAM address outputs identify the row address (CBADD12:0]) and column address (CBADD[12:0]) for the locations accessed. CBADD[12:0] is updated on the rising edge of SYSCLK.
Output
Chunk Buffer SDRAM Bank Select. The bank select signal determines which bank of a dual/quad bank Chunk Buffer SDRAM chip is active. CBBS[1:0] is generated along with the row address when CBRASB is asserted low. CBBS[1:0] is updated on the rising edge of SYSCLK.
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CBDAT[0] CBDAT[1] CBDAT[2] CBDAT[3] CBDAT[4] CBDAT[5] CBDAT[6] CBDAT[7] CBDAT[8] CBDAT[9] CBDAT[10] CBDAT[11] CBDAT[12] CBDAT[13] CBDAT[14] CBDAT[15] CBDAT[16] CBDAT[17] CBDAT[18] CBDAT[19] CBDAT[20] CBDAT[21] CBDAT[22] CBDAT[23]
I/O
AH19 AK19 AL19 AG18 AH18 AJ18 AK18 AL18 AG17 AH17 AJ17 AK17 AL17 AL15 AK15 AG15 AL14 AK14 AJ14 AH14 AG14 AL13 AK13 AJ13
Chunk Buffer SDRAM Data. The bidirectional Chunk Buffer SDRAM data bus pins interface directly with the Chunk Buffer SDRAM data ports. CBDAT[47:0] is updated/tristated on the rising edge of SYSCLK.
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CBDAT[24] CBDAT[25] CBDAT[26] CBDAT[27] CBDAT[28] CBDAT[29] CBDAT[30] CBDAT[31] CBDAT[32] CBDAT[33] CBDAT[34] CBDAT[35] CBDAT[36] CBDAT[37] CBDAT[38] CBDAT[39] CBDAT[40] CBDAT[41] CBDAT[42] CBDAT[43] CBDAT[44] CBDAT[45] CBDAT[46] CBDAT[47] Table 8
I/O
AG13 AL12 AK12 AJ12 AH12 AG12 AK11 AJ11 AH11 AL10 AK10 AJ10 AH10 AL9 AG10 AK9 AJ9 AH9 AL8 AG9 AH8 AL7 AG8 AJ7
- Microprocessor Interface Signals (44) Pin Name BCLK Type Input Pin No. G5 Function Bus Clock. This clock is the bus clock for the microprocessor interface. BCLK must cycle at 33-66 MHz instantaneous rate.
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Pin Name AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] ADSB
Type I/O
Pin No. F3 E1 F4 E2 F5 E3 D2 E4 D5 B4 C5 E6 B5 D6 A5 C6 E7 B6 D7 C7 B7 A7 D8 C8 B8 E9 A8 D9 E10 A9 D10 C10 B10
Function Multiplexed Address Data Bus. The multiplexed address data bi-directional bus AD[31:0] is used to connect the FREEDM336A1024 to the microprocessor. During the address phase when ADSB = 0, AD[1:0] are ignored as all transfers are 32 bits wide. AD[31:0] is sampled/updated/tristated on the rising edge of BCLK.
Input
Address Status. This signal is active-low and indicates a long-word address is present on the address/data bus AD[31:2]. ADSB is sampled on the rising edge of BCLK.
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Pin Name CSB
Type Input
Pin No. A10
Function Active Low Chip Select. The chip select (CSB) signal is low during the address cycle (as defined by ADSB) FREEDM336A1024 register accesses. CSB is sampled on the rising edge of BCLK.
WR
Input
D11
Write/Read. The write/read (WR) signal is evaluated when the ADSB and CSB are sampled active by FREEDM-336A1024. The BUSPOL input pin controls the polarity of this input. WR is sampled on the rising edge of BCLK.
BURSTB
Input
C11
Burst Bar. This signal is evaluated when the ADSB and CSB are sample active by FREEDM-336A1024. When low, this signal indicates that the current access is a burst access (and the BLAST input can be used to detect the end of the transaction). BURSTB is sampled on the rising edge of BCLK.
BLAST
Input
B11
Burst Last. This signal indicates the last data access of the transfer. When the BURSTB input is low, the BLAST input is driven active during the last transfer of a transaction (even if the transaction is one word in length). When the BURSTB input is high, the BLAST input is ignored by FREEDM-336A1024. The BUSPOL input pin controls the polarity of this input. BLAST is sampled on the rising edge of BCLK.
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Pin Name READYB
Type Tri-state Output
Pin No. E12
Function Ready Bar. This active low signal indicates that data on the AD[31:0] bus has been accepted (for writes), or data on the AD[31:0] is valid (for reads). This signal may be used by FREEDM-336A1024 to delay a data transaction. This output is tristated one clock cycle after an FREEDM336A1024access, allowing multiple slave devices to be tied together in the system. This output should be pulled up externally. READYB is updated on the rising edge of BCLK.
BTERMB
Tri-state Output
D12
Burst Terminate Bar. This signal is asserted low by FREEDM-336A1024 when a data transfer has reached the address boundary of a burstable range. The maximum burst range supported is 4. Attempts to extend the burst transfer after this signal is asserted will be ignored. This output is tristated one clock cycle after an FREEDM-336A1024access, allowing multiple slave devices to be tied together in the system. This output should be pulled up externally. BTERMB is updated on the rising edge of BCLK.
WRDONEB
Output
C12
Write Done Bar. This signal is asserted low by FREEDM-336A1024when the most recent write access to internal registers is complete. This signal may be used by external circuitry to delay the issuance of a write operation address cycle until FREEDM-336A1024can accept write data. This signal is only needed in systems where the READYB output cannot be used to delay a write data transaction (due to microprocessor restrictions). WRDONEB is updated on the rising edge of BCLK.
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Pin Name INTHIB
Type OD
Pin No. B12
Function Active Low Open-Drain High Priority Interrupt. This signal goes low when a FREEDM-336A1024 high priority interrupt source is active and that source is unmasked. The FREEDM-336A1024may be enabled to report many alarms or events via interrupts. INTHIB becomes high impedance when the interrupt is acknowledged via an appropriate register access. INTHIB is an asynchronous signal. Active Low Open-Drain Low Priority Interrupt. This signal goes low when a FREEDM-336A1024 low priority interrupt source is active and that source is unmasked. The FREEDM-336A1024may be enabled to report many alarms or events via interrupts. INTLOB becomes high impedance when the interrupt is acknowledged via an appropriate register access. INTLOB is an asynchronous signal. Bus Control Polarity. This signal indicates the polarity of the WR and BLAST inputs to FREEDM-336A1024. When high, the BLAST pin is active high (high indicates the last word of the burst) and the WR pin is active low (low indicates write). When low, the BLAST pin is active low (low indicates the last word of the burst) and the WR pin is active high (high indicates write). BUSPOL is sampled on the rising edge of BCLK.
INTLOB
OD
A12
BUSPOL
Input
E13
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Table 9
- Miscellaneous Interface Signals (10 pins) Pin Name SYSCLK Type Input Pin No. H1 Function The system clock (SYSCLK) provides timing for the core logic. SYSCLK is nominally a 50% duty cycle clock of frequency 100 MHz 50ppm. The active low reset signal (RSTB) signal provides an asynchronous FREEDM336A1024 reset. RSTB is an asynchronous input. When RSTB is set low, all FREEDM-336A1024 registers are forced to their default states. This signal must be held low for a minimum of 320ns. In addition, all SBI, APPI and P interface output pins are forced tristate and will remain tristated until RSTB is set high. RSTB must be asserted until the SDRAMs are out of reset. PMCTEST Input H4 The PMC production test enable signal (PMCTEST) places the FREEDM336A1024 in scan mode. PMCTEST must be tied low for normal operation (and during BIST). The DLL test enable signal (DLLTEST) places the DLL in scan mode. DLLTEST must be tied low for normal operation (and during BIST). The PMC Production SCAN_EN signal is used during scan mode. It must be tied low for normal operation. The test clock signal (TCK) provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. TMS and TDI are sampled on the rising edge of TCK. TDO is updated on the falling edge of TCK.
RSTB
Input
H3
DLLTEST
Input
H2
SCAN_EN
Input
D13
TCK
Input
G3
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Pin Name TMS
Type Input
Pin No. G4
Function The test mode select signal (TMS) controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. The test data input signal (TDI) carries test data into the FREEDM-336A1024 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor. The test data output signal (TDO) carries test data out of the FREEDM-336A1024 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output, which is inactive except when scanning of data is in progress. The active low test reset signal (TRSTB) provides an asynchronous FREEDM336A1024 test access port reset via the IEEE P1149.1 test access port. TRSTB is an asynchronous input with an integral pull up resistor. Note that when TRSTB is not being used, it must be connected to the RSTB input.
TDI
Input
H5
TDO
Tristate Output
G1
TRSTB
Input
F2
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Table 10
- Power and Ground Signals Type Power Pin No. A1 A31 B2 B30 C3 C4 C16 C28 C29 D3 D4 D16 D28 D29 E5 E11 E16 E21 E27 L5 L27 T3 T4 T5 T27 T28 T29 Function The VDD3V3 pins should be connected to a well decoupled +3.3 V DC supply. These power pins provide DC current to the I/O pads
Pin Name VDD3V3
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Pin Name VDD3V3 (Continued)
Type Power
Pin No. AA5 AA27 AG5 AG11 AG16 AG21 AG27 AH3 AH4 AH16 AH28 AH29 AJ3 AJ4 AJ16 AJ28 AJ29 AK2 AK30 AL1 AL31 B25 C13 D17 D19 E8 G2 H27 N29 N4 R4 W3 W28 AD5 AE30 AG24 AH13 AJ19 AK7
Function The VDD3V3 pins should be connected to a well decoupled +3.3 V DC supply. These power pins provide DC current to the I/O pads
VDD1V8
Power
The VDD1V8 pins should be connected to a well decoupled +1.8 V DC supply. These power pins provide DC current to the digital core.
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Pin Name VSS
Type Ground
Pin No. A2 A3 A4 A6 A11 A16 A21 A26 A28 A29 A30 B1 B3 B16 B29 B31 C1 C2 C30 C31 D1 D31 F1 F31 L1 L31 T1 T2 T30 T31 AA1 AA31 AF1 AF31 AH1 AH31 AJ1 AJ2 AJ30 AJ31
Function The VSS pins should be connected to ground. They provide a ground reference for the 3.3 V rail and a ground reference for the 1.8 V rail.
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Pin Name VSS (Continued )
Type Ground
NC
Pin No. AK1 AK3 AK16 AK29 AK31 AL2 AL3 AL4 AL6 AL11 AL16 AL21 AL26 AL28 AL29 AL30 B9 B24 C9 C17 C24 J5 J29 J30 K28 R3 U28 U29 AD29 AD30 AG22 AH15 AJ8 AJ15 AK8 AK23
Function The VSS pins should be connected to ground. They provide a ground reference for the 3.3 V rail and a ground reference for the 1.8 V rail.
No Connect
Notes on Pin Description: 1. All FREEDM-336A1024 inputs and bi-directionals present minimum capacitive loading.
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2. All FREEDM-336A1024 outputs can be tristated under control of the IEEE P1149.1 test access port, even those that do not tristate under normal operation. All outputs and bi-directionals are 3.3 V tolerant when tristated. 3. Inputs TMS, TDI and TRSTB have internal pull-up resistors. 4. Power to the VDD3V3 pins should be applied before power to the VDD1V8 pins is applied. Similarly, power to the VDD1V8 pins should be removed before power to the VDD3V3 pins is removed.
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10 FUNCTIONAL DESCRIPTION 10.1 INTERFACES 10.1.1 Scaleable Bandwidth Interconnect (SBI) Interface The Scaleable Bandwidth Interconnect is a synchronous, time-division multiplexed bus designed to transfer, in a pin-efficient manner, data belonging to a number of independently timed links of varying bandwidth. The SBI interface supported in FREEDM-336A1024 is a parallel 8 bit wide 77.76 MHz bus. Timing is communicated across the Scaleable Bandwidth Interconnect by floating data structures. Payload indicator signals in the SBI control the position of the floating data structure and therefore the timing. When sources are running faster than the SBI the floating payload structure is advanced by an octet by passing an extra octet in the V3 octet locations (H3 octet for DS3 mappings). When the source is slower than the SBI the floating payload is retarded by leaving the octet after the V3 or H3 octet unused. Both these rate adjustments are indicated by the SBI control signals. The SBI multiplexing structure is modeled on the SONET/SDH standards. The SONET/SDH virtual tributary structure is used to carry T1/J1 and E1 links. Unchannelized DS3 payloads follow a byte synchronous structure modeled on the SONET/SDH format. An SBI interface consists of a DROP BUS and an ADD BUS. On the DROP BUS all timing is sourced from the PHY and is passed onto the FREEDM-336A1024 by the arrival rate of data over the SBI. On the ADD BUS either the PHY or the FREEDM-336A1024 can control timing. When the FREEDM-336A1024 is the timing master, the PHY device determines it's transmit timing information from the arrival rate of data across the SBI. When the PHY device is the timing master, it signals the FREEDM-336A1024 to speed up or slow down with justification request signals. The PHY timing master indicates a speedup request to the Link Layer by asserting the justification request signal high during the V3 or H3 octet of the DROP bus. When this is detected by the FREEDM-336A1024 it will advance the channel by inserting data in the next V3 or H3 octet as described above. The PHY timing master indicates a slowdown request to the FREEDM-336A1024 by asserting the justification request signal high during the octet after the V3 or H3 octet of the DROP bus. The FREEDM-336A1024 responds by leaving the octet following the next V3 or H3 octet unused. Both advance and retard rate adjustments take place in the frame or multi-frame following the justification request.
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The SBI structure uses a locked SONET/SDH structure fixing the position of the TUG-3/TU-3 relative to the STS-12/STM-4 transport frame. The SBI is also of fixed frequency and alignment as determined by the reference clock (REFCLK) and frame indicator signal (AC1FP or DC1FP). Adjusting the location of the T1/J1/E1/DS3 channels using floating tributaries as determined by the V5 indicator and payload signals (DV5, AV5, DPL and APL) compensates frequency deviations. The multiplexed links are separated into twelve Synchronous Payload Envelopes. Each envelope may be configured independently to carry up to 28 T1/J1s, 21 E1s, 1 DS3 or 1 Fractional Rate DS3/E3. 10.1.2 ANY-PHY Interface The ANY-PHY Interface is an asynchronous interface that supports the transfer of data to and from the ANY-PHY channels within the FREEDM-336A1024. Two variants of the ANY-PHY interface are supported in FREEDM-336A1024: a parallel 52 MHz 16 bit wide bus (ANY-PHY Level 2), and a parallel 8 bit wide 104 MHz bus (ANY-PHY Level-3). 10.1.2.1 ANY-PHY Modes of Operation
The figures below show the different transfer formats for each mode. Datagrams are transferred across the interface as a series of continuous segments. A segment (Figure 3) consists of an address prepend and a fixed size of data. The address prepend indicates the ANY-PHY channel associated with the segment. For multilink bundles, the address prepend maps to the multilink bundle while the address prepend maps to an HDLC channel for single links. Three segment sizes are possible (64,128,and 256 bytes). The address prepend is not included in this segment size. A transfer will be terminated early if the end of packet occurs before the end of a segment. The segment size is global across the ANY-PHY interface. Minimum packet/frame size supported is 2 bytes. If the polled TPA=1, the FREEDM-336A1024 expects an entire packet to be transferred. It is not permitted to interleave the segments of packets destined for different channels. The address prepend identifies the ANY-PHY channel associated with the segment. On transmit, the FREEDM-336A1024 uses the address prepend to index ANY-PHY channel records that dictate the processing options for an ANYPHY channel. A connection identifier, in the transmit direction, is used to index connection context records that FREEDM-336A1024 uses in processing the datagram. The connection record contains various connection information including an indication if this connection is to be fragmented. A connection
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identifier must be present on all datagrams being transferred on a link that supports fragmentation or is a member of a multilink bundle (required for all modes of operation except transparent). Begin (B) and End (E) bits are used to identify the starting fragment of a packet (B=1) and the last fragment of a packet (E=1). These are needed to support FRF.12 and RFC 1990 fragment transfers across the ANY-PHY interface. When a complete packet is transferred across the interface both bits (B and E) are set to 1. It should be noted that the PID values (PID(H) and PID(L)) referenced in the following documents refers to the multilink PID = 0x003D if the connection is multilink or the PID of the actual datagram if the connection is not multlink. In the case of multlink, the first Payload data will then be the actual PID of the datagram. For uncompressed PPP packets, the FREEDM-336A1024 will accept any value of address and control fields (so as not to prohibit future changes of these values).
Figure 3 - ANY-PHY Level 2 Mode Segment Transfer - Non Sequenced Datagrams on a Link supporting sequencing (i.e. Control, LCP, NCP packets) (ingress and egress) Bits 15-8
Word 0 Word 1 Word 2 Word 3 Word 4 Word 5
Bits 7-0 Address Prepend Connection identifier (CI) Payload Data Payload Data Payload Data Payload Data * * *
0
0
Word N
Payload Data
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Figure 4 - ANY-PHY Level 2 Mode Segment Transfer - Non-Header Segment (i.e. not first segment of a datagram) or Transparent Mode (ingress and egress) Bits 15-8
Word 0 Word 1 Word 2 Word 3 Word 4 Word 5
Bits 7-0 Address Prepend Payload Data Payload Data Payload Data Payload Data Payload Data * * *
Word N
Payload Data
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ANY-PHY Level 2 Mode - Figure 5 - Figure 10 illustrate the transfer requirements for the various transfer types using this mode. Figure 5 - ANY-PHY Level 2 Mode Header Segment - PPP over sequenced link (ingress and egress) Bits 15-8
Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6
Bits 7-0 Address Prepend Connection Identifier (CI)
B
E Address PID(H)
Control PID(L) Payload Data Payload Data Payload Data * * *
Word N
Payload Data
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Figure 6 - ANY-PHY Level 2 Mode Header Segment - FR over sequenced link (ingress and egress) Bits 15-8
Word 0 Word 1 Word 2
Bits 7-0 Address Prepend Connection Identifier (CI)
B
E DLCI (msb)
C/ E RA = 0
DLCI (lsb)
F E C N
B E C N
D E
E A = 1
Word 3 Word 4 Word 5 Word 6
Payload Data Payload Data Payload Data Payload Data * * *
Word N
Payload Data
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Figure 7 illustrates the first segment of a datagram on the receive interface when the system side device receiving the segments supports fragmentation. In this application, the sequence number of the fragment is appended to the PPP header as defined in RFC 1990. This allows the system side device to detect lost fragments. Figure 7 - ANY-PHY Level 2 Mode Header Segment - ML- PPP with Fragments out (Ingress Only) Bits 15-8
Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6
Bits 7-0 Address Prepend Connection Identifier (CI)
B
E Address PID(H)
Control PID(L) 0 0 Sequence Number (Long)
B
E
COS (3:0)
Sequence Number (Long) Payload Data Payload Data Payload Data * * *
Word N
Payload Data
For short Sequence numbers, Words 4 and 5 get replaced with one word: B E
COS(1:0)
Sequence Number (Short)
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Figure 8 - Figure 10 are representative of packets with PPP header compression being performed. Figure 8 - ANY-PHY Level 2 Mode Header Segment - PPP over a sequenced link with Address and Control Field Header Compression (ingress and egress) Bits 15-8
Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
Bits 7-0 Address Prepend Connection Identifier (CI)
B
E PID(H)
PID(L) Payload Data Payload Data Payload Data Payload Data Payload Data * * *
Word N
Payload Data
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Figure 9 - ANY-PHY Level 2 Mode Header Segment - PPP over a sequenced link with PID Header Compression (ingress and egress) Bits 15-8
Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
Bits 7-0 Address Prepend Connection Identifier (CI)
B
E Address PID(L)
Control Payload Data Payload Data Payload Data Payload Data Payload Data * * *
Word N
Payload Data
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Figure 10 - ANY-PHY Level 2 Mode Header Segment - PPP over a sequenced link with Address /Control Field and PID Header Compression (ingress and egress) Bits 15-8
Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6
Bits 7-0 Address Prepend Connection Identifier (CI)
B
E PID(L)
Payload Data Payload Data Payload Data Payload Data Payload Data * * *
Word N
Payload Data
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ANY-PHY Level 3 mode. Figure 11 shows how words are transferred as bytes and Figure 12 gives an example of such a transfer. All transfer types shown in Level-2 are also supported in Level-3. Figure 11 - ANY-PHY Level 3 Mode Segment - Transparent or NonHeader Segment (ingress and egress) Bits 7-0
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
Address Prepend [15:8] Address Prepend [7:0] Payload Byte 0 Payload Byte 1 Payload Byte 2 Payload Byte 3 Payload Byte 4 Payload Byte 5
* * *
Byte N
Payload Byte N
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Figure 12 - ANY-PHY Level 3 Mode Header Segment - FR over a sequenced link (ingress and egress) Bits 7-0
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
Address Prepend [15:8] Address Prepend [7:0] B E CI[13:8] CI[7:0] DLCI (msb) C/ E RA = 0 B E C N D E E A = 1
Byte 5
DLCI (lsb)
F E C N
Byte 6 Byte 7 Byte 8 Byte 9
Payload Byte 0 Payload Byte 1 Payload Byte 2 Payload Byte 3
* * *
Byte N
Payload Byte N
10.2 Memory Port 10.2.1 Writing Write operations to external memory can be performed in up to 4-long word bursts to the memory port. The procedure is as follows: 1. The microprocessor polls the MPBusy bit of the Memory Port Control register (or monitors the MPISTATI interrupt) to verify that the previous write is complete. Alternatively, this step may be skipped if the system application allows FREEDM-
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336A1024 to withhold the READYB for write accesses. In this case, FREEDM336A1024 will delay write operations to the write burst registers and overflow register until the previous write command is complete. 2. The microprocessor writes up to 4 long words of data into the write burst register array and the overflow register (for 48-bit accesses). 3. The microprocessor writes a command to the memory burst control register. The command indicates the aperture, the quad-long word address in memory, the type of write (masked or unmasked), and the 4 long word enables. MPBusy will be set until the write is complete. 4. FREEDM-336A1024 arbitrates for the appropriate memory, performs the write to memory, and clears the MPBusy bit in the control register. 10.2.2 Reading Reads from external memory can be performed in 4-long word bursts from the memory port. The procedure is as follows: 1. The microprocessor issues a read command to the Memory Port Control register. The command indicates aperture, the quad-long word address in memory, and 4 long word enables. The MPBusy bit will be set by the FREEDM-336A1024. 2. FREEDM-336A1024 arbitrates for the appropriate memory, performs the read from memory and loads the read burst registers with the results, and clears the MPBusy bit in the control register. 3. The microprocessor polls the MPBusy bit of the Memory Port Control register status (or monitors the MPISTATI interrupt) to verify that the read is complete. Alternatively, this step may be skipped if the system application can tolerate long response times for read accesses. In this case, FREEDM-336A1024 will delay read operations from the read burst registers and overflow register until the read command is complete. 4. The microprocessor reads up to 4 long words of data from the read burst register array and the overflow register (for 48-bit accesses). 10.3 PACKET WALKTHROUGH 10.3.1 Ingress Path Figure 13 shows the elements and data transformations that occur as data transmits the FREEDM-336A1024 from the SBI to the ANY-PHY interface.
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Figure 13
- Ingress Data Flow
ANY PHY I/F
EXSBI336
Channel -izer
Partial HDLC Packet Processor
Cache RFRAG BUILDER
Frame DLCI RE-SEQ Builder Lookup
INGRESS
Q
MANAGER
Bitstreams per link Bytes per HDLC Channel Block per HDLC Channel
Priority queues (2)
Linked list of Chunks per HDLC Channel (fragment)
Linked list of Chunks Placed in re-sequencing Order
Data arriving via the SBI interface is extracted from the SBI format and associated with an HDLC channel. In addition to the SBI bus, 12 clock and data interfaces are also supported simultaneously. Each link is independent and has its own associated clock. For each link, a serial to parallel conversion forms the data bytes. The data bytes are multiplexed, in byte serial format, for delivery to the HDLC/Partial Packet Processor block The HDLC engine receives the incoming byte stream and examines the byte stream to delineate the opening and closing of the HDLC packet. Bit de-stuffing is performed, FCS checking and minimum/maximum packet size checking is performed. The HDLC engine is capable of simultaneously processing 1024 independent HDLC channels. The resulting HDLC data and status information is passed to the Partial Packet Processor to be stored in the appropriate HDLC channel FIFO buffer. The Partial Packet Processor controls a 64 Kbyte partial packet RAM. Data is written into the RAM at a location that is associated with the HDLC channel. As
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more data arrives for a given HDLC channel, it is stored with the previous bytes of data for a given HDLC channel forming a chunk of data. Packets are not intermingled within chunks. Completed chunks are passed to the fragment builder. Fragments are defined as per FRF.12 and RFC 1990. The chunk is stored in external SDRAM in a data structure that is indexed on a per datagram basis. The fragment builder can simultaneously reconstruct 1024 datagrams (one per HDLC channel). Completed datagrams are forwarded to the lookup and re-sequencing stage. This stage performs a header lookup that is used to determine connection identifier. A connection record associated with the CI contains a number of state variables used in the re-sequencing operation and to guide the remaining ingress operations for the datagram. Re-sequencing is required when ML-FR or ML-PPP is active on a given set of HDLC channels. Given the variable length of data transfers and skew between the physical links in the multilink bundle, resequencing is essential to enabling multilink protocols. Both 12 and 24 bit sequence numbers are supported for PPP while the 12 bit FRF.12 format is supported for FR. The incoming sequence number is compared with the expected sequence number. If the two are equal, the datagram does not need to be re-sequenced and is logically passed to the ingress queue or the packet/frame builder depending on the style of data transfer (packet or fragment) requested for the ANY-PHY channel. If the sequence numbers do not align, a re-sequencing operation is triggered and the datagram is logically placed in the re-sequencing buffers. The datagram is removed from the re-sequencing buffers when the re-sequencing operation has correctly re-sequenced the datagrams. These datagrams are passed to the frame builder or the ingress queue manager depending on the mode of transfer. In addition to re-sequencing, a loss detection algorithm detects lost datagrams. When the ANY-PHY transfer is frame/packet based, the frame builder constructs complete frames or packets from the datagrams that have been constructed by the fragmentation builder. These complete frames/packets are transferred to the ingress queue manager. The ingress queue manager arbitrates between the packets/frames and fragments that are available to be sent. The resulting decision is passed to the ANY-PHY interface. The selected fragment/packet is transferred to the upstream system device via the ANY-PHY interface.
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10.3.2 Egress Path Figure 14 shows the elements and data transformations that occur as data transmits the FREEDM-336A1024 from the ANY-PHY to the SBI interface. Figure 14 - Egress Data Flow
INSBI336
DeChannelizer
Partial HDLC Packet Processor
Egress Queue Manager
TFRAG Builder
ANY PHY I/F
Bitstreams per link Bytes per HDLC Channel Block per HDLC Channel
Full packets or fragments can be transferred from the upstream device to the FREEDM-336A1024 via the ANY-PHY interface. When supporting a multilink bundle, the ANY-PHY channel is mapped to multiple HDLC channels. The transmit fragmentor will fragment packets/frames and distribute the fragments across all the HDLC channels in the multilink bundle applying the appropriate sequence number to each of the fragments. The fragmentation size is programmable on a per multilink bundle basis. The fragmentation size is referenced to the number of bytes transferred on the link and includes the multilink header. On an HDLC channel basis the datagrams are decomposed into chunks and are stored in an external SDRAM memory. A chunk is defined as a fixed length unit
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of data (32 bytes) plus a 4 byte header, or a partially completed unit of data. A chunk will only consist of data from one packet/frame. The chunk transmitter controls a 64 Kbyte partial packet RAM. A data chunk is transferred from external memory into the partial packet RAM in a burst. Data is read from the RAM a byte at a time and delivered to the HDLC engine. The chunk transmitter can support 1024 simultaneous byte transfer sessions (one per HDLC channel). As chunks are depleted, the chunk transmitter requests the next chunk for the associated HDLC channel from the fragment transmitter. The HDLC engine receives the incoming byte stream and encapsulates the data stream with a HDLC header, bit stuffing and a FCS trailer. The HDLC engine is capable of simultaneously processing 1024 independent HDLC channels. The resulting HDLC data and status is passed to the de-channelizer to be transferred onto the links. Data arriving at the SBI interface is inserted into the SBI format at the correct tributary and timeslot associated with a HDLC channel. In addition to the SBI bus, 12 clock and data interfaces are also supported. 10.4 Loopback 10.4.1 Clock and Data Loopback The line loopback enable bits in the Master Line Loopback Register control line loopback for the twelve serial clock and data links #11 to #0. When loopback is enabled, the data on RD[n] is passed verbatim to TD[n], which is then updated on the falling edge of RCLK[n]. TCLK[n] is ignored. When loopback is disabled, TD[n] is processed normally. 10.4.2 SBI Line Loopback When enabled, the data on tributary #n output by the EXSBI336 block is looped back to the tributary #n in the INSBI336 block. When loopback is disabled, transmit data for tributary #n is provided by the TCAS-12 block (i.e. processed normally).
10.4.3 System Side Loopback The loopback controller block in the RCAS-12 TSB implements the channel based diagnostic loopback function. Every valid data byte belonging to a channel with diagnostic loopback enabled from the Transmit HDLC Processor /
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Partial Packet Buffer block (THDL-12) is written into a 1024 word FIFO in the RCAS-12 block. The loopback controller monitors for an idle time-slot or a timeslot carrying a channel with diagnostic loopback enabled. If either condition holds, the current data byte is replaced by data retrieved from the loopback data FIFO. 10.5 Initialization Process 10.5.1 CB and RS Memory FPP Initialization 1. After a hardware or software reset is issued, the chip goes into an initialization sequence. The RST_DONEI bit in the F336 Master High Priority Interrupt Status register will indicate when this sequence is complete. At this stage, all the registers and memories internal to the chip and the external SRAM can be accessed. 2. Wait for SDRAM_INIT to be cleared in XX_DRAMC Status and Control Registers (PROV_MODE will also be set at this point). 3. Test memories if desired by s/w. 4. FPP FIFO Initialization * Option 1 (s/w init) * write ECC_OFF bit as desired * write to the memory setting up the FPP FIFO as described in the XX_DRAMC memory map descriptions * write FUNC_MODE=1 and PROV_MODE=0 in the XX_DRAMC Status and Control Registers * Option 2 (h/w init) * write ECC_OFF bit to 1 * write FPP_INIT bit =1 and PROV_MODE=0 in the XX_DRAMC Status and Control Registers * wait for FUNC_MODE to be set indicating completion (PROV_MODE will also be cleared) 5. Initialization Complete 10.5.2 Connection Initialization for sequenced links When adding a connection to a multilink bundle (including first connection setup), the specification does not dictate that the first sequence number sent must start at any particular value. As a result, the Freedm-336A1024 takes the first sequence number it receives to start re-sequencing. Due to differential delay between links, if this isn't the fastest link, this might not be the start of packet. All subsequent fragments with lower sequence numbers will not be included in the re-sequencing and will be sent out the ANY-PHY tagged as unexpected sequence number. The number of packets tagged as
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USN will depend on packet size and egress scheduling algorithm. Once the first resequenced packet is complete (if in packet out mode), this packet will be sent out missing the first few fragments but will not be tagged as erred. This will happen with every new connection. In order to avoid this, one of the following can be done: 1. Ensure the first fragment is sent down the fastest link. 2. Send the first fragment down any link and wait a time period equal to the worst case link skew but less than the programmed lost timeout period before sending the second fragment. 10.6 ANY-PHY Tear Down Procedure Before tearing down an ANY-PHY channel, all CI's associated with that ANY-PHY channel must be torn down according to the procedure described in section 10.7. 10.7 CI Tear Down Procedure A CI tear-down procedure must be followed when decommissioning an active CI to avoid loss of resources shared among all active CIs. Since the decommissioned CI continues to hold up to one LSB record, the algorithm that assigns active CI's from the pool of inactive CI's should recycle previously used CI's before assigning a previously unused CI. This will result in the best use of shared resources. The tear-down procedure is comprised of the following seven steps: 1. Remove the CI from the CI Lookup table to ensure no additional datagrams are received for the CI undergoing decommissioning 2. Read the Resequencing Active (RESEQ_ACT) bit and the FIFO Active (FIFO_ACT) bit in the connection context memory for the CI. If both bits are inactive skip the next two steps 3. If resequencing is flagged as active set the Lost Timeout Period (LOST_CNT) register to "0001" in the connection context memory for the CI 4. Periodically read the RESEQ_ACT and FIFO_ACT bits until both are inactive 5. Read the MSB record associated with the CI and extract the valid LSB record pointer, if applicable. To identify a valid LSB record pointer within the MSB record structure all 128 locations of the MSB record must be read and th examined. Bit 15, the 16 bit, of each 32-bit data word returned indicates whether the lower 15-bits identify a valid LSB record pointer (LSB_POINTER). Up to one pointer may be valid. This pointer is used to
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determine what LSB status locations to clear for the CI being decommissioned. An MSB record is extracted from the external resequencing SDRAM memory by reading 128 consecutive locations beginning at the address as determined by the following equation: MSB Record begin address = 800,000H + CI_number x 80H. 6. If applicable, clear the LSB status for the active LSB record. Each 32-bit location within the LSB record status field contains status for 16 datagrams. Therefore to clear the status for the entire 128-location LSB record, 8 LSB status locations must be cleared to zero. The 8 consecutive locations requiring clearing begin at the address determined by the following equation: LSB status begin address = 400,000H + LSB_POINTER x 8H. 7. Clear connection context memory for the CI. At this point tear-down is completed
10.8 Restrictions on ANY-PHY to CI mapping * For proper operation, 1. Both the control and corrupt CI look-up locations for each HDLC channel should each be assigned a unique CI number. Unique meaning each of the CI numbers should only appear once in the CI look-up table. 2. A CI number may be shared among various COS/DLCIs within either a single HDLC channel, or HDLC channels of a ML bundle, but must not be re-used outside of the single HDLC channel or the ML bundle. 3. HDLC channels of a ML bundle must map to the same ANY-PHY channel. * For the highest level of robustness 1. For robustness, in the presence of errors undetected by HDLC CRC, a unique CI number, per HDLC channel, should be populated for all unused sequenced-CI look-up locations. Also, a unique CI number, per HDLC channel, should be populated for all unused non-sequenced-CI look-up locations.
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10.9 BLOCK DESCRIPTIONS 10.9.1 Extract Scaleable Bandwidth Interconnect (EXSBI336) The SBI Extract block receives data from the SBI DROP BUS and converts it to an internal parallel bus format. The SBI Extract block may be configured to enable or disable reception of individual tributaries within the SBI DROP bus. Individual tributaries may also be configured to operate in framed or unframed mode. Tributaries may be configured to support channelized T1/J1/E1 traffic, unchannelized DS3 or Fractional Rate DS3/E3 traffic or unframed traffic at T1/J1, E1 or DS3 rates. 10.9.2 Receive Channel Assignor (RCAS-12) The Receive Channel Assignor block (RCAS-12) processes up to 336 links. When receiving data from the SBI blocks, links may be configured to support channelized T1/J1/E1 traffic, unchannelized DS3 traffic or unframed traffic at T1/J1, E1, DS3 or Fractional DS3 rates. When receiving data from the RD inputs, links 0, 1 through 11 support unchannelized data at arbitrary rates up to 52 Mbps. It should be noted that for every SBI/SPE used as a serial link, the SBI/SPE must be disabled on the SBI Bus interface and visa versa. Each link is independent and has its own associated clock. When receiving data from the RD inputs, the RCAS-12 performs a serial to parallel conversion to form data bytes. The data bytes are multiplexed, in byte serial format together with data from EXSBI336, for delivery to the Receive HDLC Processor / Partial Packet Buffer block (RHDL-12) at SYSCLK rate. In the event when multiple streams have accumulated a byte of data, multiplexing is performed on a fixed priority basis with link #0 having the highest priority and link #335 the lowest. The 336 RCAS links have a fixed relationship to the SPE and tributary numbers on the SBI DROP BUS as shown in the following table. Table 11 SBISPE No. 1-1 1-2 1-3 SBI Trib. No. 1 1 1 RCAS Link No. 0 4 8 - SBI SPE/Tributary to RCAS Link Mapping SBISPE No. 2-1 2-2 2-3 SBI Trib. No. 1 1 1 RCAS Link No. 1 5 9 SBISPE No. 3-1 3-2 3-3 SBI Trib. No. 1 1 1 RCAS Link No. 2 6 10 SBISPE No. 4-1 4-2 4-3 SBI Trib. No. 1 1 1 RCAS Link No. 3 7 11
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SBISPE No. 1-1 1-2 1-3 1-1 1-2 1-3 l l l 1-1 1-2 1-3
SBI Trib. No. 2 2 2 3 3 3
RCAS Link No. 12 16 20 24 28 32
SBISPE No. 2-1 2-2 2-3 2-1 2-2 2-3
SBI Trib. No. 2 2 2 3 3 3 l l l
RCAS Link No. 13 17 21 25 29 33
SBISPE No. 3-1 3-2 3-3 3-1 3-2 3-3
SBI Trib. No. 2 2 2 3 3 3 l l l
RCAS Link No. 14 18 22 26 30 34
SBISPE No. 4-1 4-2 4-3 4-1 4-2 4-3
SBI Trib. No. 2 2 2 3 3 3
RCAS Link No. 15 19 23 27 31 35 l l l
28 28 28
324 328 332
2-1 2-2 2-3
28 28 28
325 329 333
3-1 3-2 3-3
28 28 28
326 330 334
4-1 4-2 4-3
28 28 28
327 331 335
Links containing a T1/J1 or an E1 stream may be channelized. Data at each time-slot may be independently assigned to a different HDLC channel. The RCAS-12 performs a table lookup to associate the link and time-slot identity with an HDLC channel. The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse signals generated by the EXSBI336. Links containing a DS3 stream are unchannelized, i.e. all data on the link belongs to one HDLC channel. The RCAS-12 performs a table lookup using only the link number to determine the associated HDLC channel, as time-slots are non-existent in unchannelized links. Links may additionally be configured to operate in an unframed "clear channel" mode, in which all bit positions, including those normally reserved for framing information, are assumed to be carrying HDLC data. Links so configured operate as unchannelized regardless of link rate and the RCAS-12 performs a table lookup using only the link number to determine the associated HDLC channel. All timeslots in a link must be provisioned to a valid channel number before the link is enabled. For unused timeslots, a valid unused channel number must be set but the PROV bit is not set. All unused timeslots in the device can be mapped to the same unused channel number. When unprovisioning a channel, the INVERT bit in register 0x208 must be cleared (if set), The PROV bit is then set to 0 but the channel number must be written back into the channel number field. This will flush out any data on this channel still present in the chip. This sequence must occur before the link is disabled.
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The loopback controller block implements the channel based diagnostic loopback function. Every valid data byte belonging to a channel with diagnostic loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer block (THDL-12) is written into a 1024 word FIFO. The loopback controller monitors for an idle time-slot or a time-slot carrying a channel with diagnostic loopback enabled. If either condition holds, the current data byte is replaced by data retrieved from the loopback data FIFO.
10.9.3 Receive HDLC Protocol Engine (RHDL-12) The HDLC engine receives the incoming byte stream and examines the stream to determine the opening and closing of the HDLC packet. Bit de-stuffing, FCS checking and minimum/maximum packet size checking is performed. The HDLC engine is capable of simultaneously processing 1024 independent HDLC channels. The resulting HDLC data and status information is passed to the Partial Packet Processor to be stored in the appropriate HDLC channel FIFO buffer. Figure 15 shows a diagram of the synchronous HDLC protocol supported by the FREEDM-336A1024 device. The incoming stream is examined for flag bytes (01111110 bit pattern) that delineate the opening and closing of the HDLC packet. The packet is bit de-stuffed which discards a "0" bit which directly follows five contiguous "1" bits. The resulting HDLC packet size must be a multiple of an octet (8 bits) and within the expected minimum and maximum packet length limits. The minimum packet length is that of a packet containing two information bytes (address and control) and FCS bytes. For packets with CRC-CCITT as FCS, the minimum packet length is four bytes while those with CRC-32 as FCS; the minimum length is six bytes. An HDLC packet is aborted when seven contiguous "1" bits (with no inserted "0" bits) are received. At least one flag byte must exist between HDLC packets for delineation. Contiguous flag bytes, or all ones bytes between packets are used as an "inter-frame time fill". Adjacent flag bytes may share zeros. Figure 15
Flag
- HDLC Frame
Information HDLC Packet FCS Flag Flag
The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. Figure 16 shows a CRC encoder block diagram using the generating polynomial g(X) = 1 + g1X + g2X2 +...+ gn-1Xn-1 + Xn. The CRC-CCITT FCS is two bytes in size and has a generating polynomial
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g(X) = 1 + X5 + X12 + X16. The CRC-32 FCS is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X26 + X32. The first FCS bit received is the residue of the highest term. Figure 16 - CRC Generator
g1
g2
gn-1 Message
D0
D1
D2
Dn-1
LSB
Parity Check Digits
MSB
10.9.3.1
Partial Packet Buffer Processor
The partial packet buffer processor controls the 64 Kbyte partial packet RAM, which is divided into 4K 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular HDLC channel FIFO buffers. Thus, noncontiguous sections of the RAM can be allocated in the partial packet buffer RAM to create an HDLC channel FIFO. System software is responsible for the assignment of blocks to individual HDLC channel FIFOs. Figure 17 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte HDLC channel FIFO.
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Figure 17
- Partial Packet Buffer Structure Partial Packet Buffer RAM Block Pointer RAM
Block 0 Block 1 Block 2 Block 3 XX 0x03 XX 0xC8
Block 0 Block 1 Block 2 Block 3
16 bytes 16 bytes 16 bytes 16 bytes
Block 200
16 bytes
Block 200
0x01
Block 4095
16 bytes
Block 4095
XX
The partial packet buffer processor is divided into three sections: writer, reader and roamer. The writer is a time-sliced state machine that writes the HDLC data and status information from the HDLC processor into a channel FIFO in the packet buffer RAM. The reader transfers HDLC channel FIFO data from the packet buffer RAM to the downstream fragment builder block (RFRAG). The roamer is a time-sliced state machine that tracks HDLC channel FIFO buffer depths and signals the reader to service a particular HDLC channel. If a buffer over-run occurs, the writer ends the current packet from the HDLC processor in the HDLC channel FIFO with an overrun flag and ignores the rest of the packet. The FIFO algorithm of the partial packet buffer processor is based on a programmable per-HDLC channel transfer size. Instead of tracking the number of full blocks in an HDLC channel FIFO, the processor tracks the number of transactions. Whenever the partial packet writer fills a transfer-sized number of blocks or writes an end-of-packet flag to the HDLC channel FIFO, a transaction is created. Whenever the partial packet reader transmits a transfer-size number of blocks or an end-of-packet flag to the RFRAG block, a transaction is deleted. Thus, small packets less than the transfer size will be naturally transferred to the
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RFRAG block without having to precisely track the number of full blocks in the HDLC channel FIFO. The partial packet roamer performs the transaction accounting for all HDLC channel FIFOs. The roamer increments the transaction count when the writer signals a new transaction and sets a per-HDLC channel flag to indicate a nonzero transaction count. The roamer searches the flags in a round-robin fashion to decide for which HDLC channel FIFO to request transfer by the RFRAG block. The roamer informs the partial packet reader of the HDLC channel to process. The reader transfers the data to the RFRAG until the HDLC channel transfer size is reached or an end of packet is detected. The reader then informs the roamer that a transaction is consumed. The roamer updates its transaction count and clears the non-zero transaction count flag if required. The roamer then services the next HDLC channel with its transaction flag set high. The writer and reader determine empty and full FIFO conditions using flags. Each block in the partial packet buffer has an associated flag. The writer sets the flag after the block is written and the reader clears the flag after the block is read. The flags are initialized (cleared) when the block pointers are written using indirect block writes. The writer declares an HDLC channel FIFO overrun whenever the writer tries to store data to a block with a set flag. In order to support optional removal of the FCS from the packet data, the writer does not declare a block as filled (set the block flag nor increment the transaction count) until the first double word of the next block in the HDLC channel FIFO is filled. If the end of a packet resides in the first double word, the writer declares both blocks as full at the same time. When the reader finishes processing a transaction, it examines the first double word of the next block for the end-ofpacket flag. If the first double word of the next block contains only FCS bytes, the reader would, optionally, process next transaction (end-of-packet) and consume the block, as it contains information not transferred to the RFRAG block. 10.9.4 Receive Fragment builder (RFRAG) The receive fragment builder re-constructs datagrams from the incoming data stream, moves data chunks from the partial packet processor into external memory, and manages the assignment of free external memory addresses to data chunks. The receive fragment builder also discards either small datagrams when an excessive number of datagrams are waiting to be processed by the resequencer, or any datagram when an ANY-PHY channel's chunk storage allocation has been exceeded. The external chunk buffer memory is partitioned into data units called chunks. A chunk is a block (36 bytes) of contiguous memory used to store parts of the data frames. Associated with each chunk is an address that is used to index the
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chunk. The addresses are stored in the external memory in a free list FIFO. The Free list FIFO contains addresses of all the chunks that are available for the storage of data. A chunk of data is unavailable when the data stored within the chunk is part of a datagram that is being actively processed by the FREEDM336A1024. Chunks become available when the FREEDM-336A1024 completes the processing of the data in the chunk (i.e. the datagram is transferred across the ANY-PHY interface to the rest of the system). Fragments are defined as per FRF.12 or RFC 1990. This block can also support the creation of complete packets or frames if the HDLC channel is configured to Frame Relay or PPP modes. This can be supported on all 1024 HDLC channels simultaneously. Data received from the partial packet RAM is encapsulated (Figure 18). The encapsulation contains the next address pointer, Last and Full flags, Error codes and an error correction code that covers the encapsulation header. The next address pointer is used to create a linked list of chunks that comprise a datagram (Figure 19).The address indicates where the next chunk of the datagram is located in the external memory. This effectively links the chunks of a datagram in external memory. The last flag is used to tag the last chunk of a datagram. The full flag indicates if the chunk contains 32 bytes of data. If the data chunk of a datagram is partially filled, the full flag is false and the number of valid bytes in the chunk is inserted in byte 0. The error codes are used to capture HDLC or RFRAG processing errors that have occurred. The error codes are provided to the system via the ANY-PHY interface enabling the system to observe the behavior of the HDLC channels. The Partial packet RAM also passes the associated HDLC channel ID, End of datagram indication, and error flags (Bad FCS, Abort, etc.). The HDLC channel ID is used to index a data record that provides the next chunk pointer. This data record is also used to store frame relay header bits (Sequence number, DLCI, BE, FE, DE, B, E, C) or PPP header bits (Address, Control, PID, COS, and Sequence number, B, E), and the address of the first chunk in the datagram. These header fields are passed to the frame builder after the last chunk in a given datagram is stored. Header bits are extracted from the first data chunk of a datagram. Corrupted datagrams are tagged and the starting address is passed forward to the re-sequencer. The RFRAG can be configured to accept compressed PPP headers. The RFRAG will correctly interpret the compressed header, and extract the information required for downstream processing from the packet. The encapsulated data chunk, and an address pointer are passed to the DRAMC controller for storage in external SDRAM. The address pointer is contained in the HDLC channel record and points to the memory location that is placed in the next address pointer field of the previous data chunk for a given datagram. The
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initial chunk of a datagram is stored at an address location, (starting address of the datagram). Datagrams may also be discarded before they are stored in the external SDRAM. When there are too many datagrams waiting to be processed by the re-sequencer, any datagram smaller than either a default 40-byte limit, or a programmable 0 to 56-byte threshold, will be discarded, except if it is tagged as the last fragment of a multi-fragment frame/packet. Furthermore, each ANY-PHY channel has a limit in the maximum number of chunks that it can have stored in the external SDRAM at any time. If this limit is exceeded, all datagrams for this ANY-PHY channel will be discarded until the number of chunks stored in the external SDRAM is reduced below the limit. The free list FIFO is stored in external memory. To reduce the accesses to external memory, an address cache is used to hold addresses that can be used for next pointer values. When a chunk is encapsulated, the HDLC channel record will fetch, from the local cache, an address that can serve as the next address for the following data chunk in the datagram. As chunks are retrieved from the external memory for the address is returned to the cache. When the cache needs to be replenished, a request is made to the DRAMC. A set of new addresses is provided from external memory. The external read request is triggered off of a threshold. When the internal Cache crosses the threshold, it requests a read from external memory.
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Figure 18
- Encapsulated Chunk Structures
a) Encapsulated Chunk Structure (Full = True) Byte 1 Byte 7 Byte 13 Byte 19 Byte 25 Byte 31 Byte 0 Byte 6 Byte 12 Byte 18 Byte 24 Byte 30 ECC(8) Byte 5 Byte 11 Byte 17 Byte 23 Byte 29 L F EC(3) NXT_CHUNK_PTR(19) Byte 4 Byte 3 Byte 2 Byte 10 Byte 9 Byte 8 Byte 16 Byte 15 Byte 14 Byte 22 Byte 21 Byte 20 Byte 28 Byte 27 Byte 26
b) Encapsulated Chunk Structure (Full = False) Byte 0 Byte 6 Byte 12 Byte 18 Byte 24 Byte 30 Size Byte 5 Byte 11 Byte 17 Byte 23 Byte 29 ECC(8) Byte 4 Byte 10 Byte 16 Byte 22 Byte 28 L F EC(3) NXT_CHUNK_PTR(19) Byte 3 Byte 2 Byte 1 Byte 9 Byte 8 Byte 7 Byte 15 Byte 14 Byte 13 Byte 21 Byte 20 Byte 19 Byte 27 Byte 26 Byte 25
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Figure 19
- Linked list data structure of a Datagram
Starting Address
Address of 1st chunk in Datagram (stored on a per HDLC channel basis)
Next address pointer Last = False; Full = True
1st chunk in Datagram
Next address pointer Last = False; Full = True
2nd chunk in Datagram
Next address pointer Last = True; Full = False Size = 3
Last chunk in Datagram
10.9.5 Frame Builder (FRMBLD) To build frames/packets from fragments requires several steps. The specific multilink/single session has to be identified, re-sequencing (for multilink sessions) followed by the actual frame/packet building are the key steps in this process. 10.9.5.1 Connection identification
The header of the datagram is used to index internal record structures needed to support re-sequencing, and ingress queuing. A lookup is used for HDLC channels supporting the Frame Relay protocol. The objective is to reduce the HDLC channel (10 bits), the DLCI (10bits), the corrupt bit and frag bit to a 14-bit CI. The HDLC channel number is concatenated with a bit indicating if the datagram is corrupt or valid, a bit indicating if the datagram is
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a control datagram, a bit indicating if the datagram is sequenced or non sequenced. This value is then concatenated with the DLCI(1-1024) for sequenced and non sequenced datagrams to produce an index into the SSRAM memory. Contained at the memory location is the 14 bit CI. For PPP header identification, the HDLC channel number is concatenated with a bit indicating if the datagram is corrupt or valid, a bit indicating if the datagram is an NCP or LCP datagram, a bit indicating if the datagram is sequenced or non sequenced. This value is then concatenated with the COS (1-16) for sequenced and non sequenced datagrams to produce an index into the SSRAM memory. Contained at the memory location is the 14 bit CI. Unique CI's must be used for each HDLC channel. 10.9.5.2 Re-Sequencing builder
The Re-Sequencing blocks provide the logic and data structures necessary to support the operations needed to support the re-ordering of ingress datagrams. These include detection of lost or out of bound datagrams, the placement of sequences in the correct order, construction of frames/packets out of fragments, and transfer the resequenced/reassembled frames/packets to the ingress queue manager. Figure 20 - The elements in the Re-sequencing block
Frame Building Logic
Loss/Out-ofSequence Detection
Channel Size Comparison
Resequencing List Addition
Frame/ Fragment Removal
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10.9.5.3
Loss Detection/Out of bounds checking
The loss detection block is based on the use of timers. Timers associated with each resequencing session would be used to detect the lost datagram and advance the resequencing engine. Each multilink re-sequencing session has an associated timer. When the multilink session transmits from in sequence to out of sequence, a timer is started. This timer is cleared when the session returns to being in sequence. All timers are periodically polled to detect sessions that have been out of sequence for an extended period of time. 10.9.5.4 Size Comparison/Timers
The chunk buffer and re-sequencing structures are shared resources. To ensure that a multilink bundle or HDLC channel does not consume more than an allocated amount of resources the number of bytes in the bundle or channel is compared against a threshold (allocated bytes). If the threshold is exceeded, the datagram is discarded. The primary reasons for exceeding the threshold are loss of a link within a member bundle or a number of ML-FR DLCIs losing datagrams. The first situation would cause the re-sequencing engine to stall on the first lost datagram. Incoming fragments from other links would then build up and create a backlog of datagrams. 10.9.5.5 Re-sequencing List addition
Datagrams that have not been discarded are entered in the re-sequencing list. The resequencing algorithm in FREEDM-336A1024 supports the worst case number of packets on a multilink bundle of T1/E1s that have experienced an intra skew delay of 100ms. To support that a subset of the 24-bit sequence number space is supported. Fourteen of the 24 bits are used for re-sequencing. All 12 bits are used when supporting 12 bit sequence numbers. On initialization, the Head Sequence number is set to the sequence number of the first fragment received. Subsequent sequence numbers are discarded if they are less than the Head Sequence number. Arriving datagrams are placed in the sliding window with an offset determined by distance (difference) between the sequence number at the head of the window and the current sequence number.
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Figure 21
- The 14-bit sliding window used for re-sequencing
Unpopulated sequence # has Null tag on it.
Fragment to be added: Location = channel_offset + (seq# - head_seq#)
Head Seq#
14 bits of the sequence number Apply a sliding window across the 24 Sequence number space Insert elements based on an offset of the head sequence number.
The sliding window (Figure 21) is realized as a two tiered data structure (Figure 22). This is done to reduce the memory required to support 16K simultaneous multilink sessions. The initial tier is present for all multilink sessions. Secondary tiers are added and removed when needed. The number of second tiers is limited. Enough are provided to support the simultaneous resequencing on all multilink sessions.
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Figure 22
- The elements in the Re-sequencing block
Datagram to be added Location = (channel_offset + Seq# - head_seq#)/128
1st tier (128 entries)
Fragment to be added location = channel_offset + seq#- head_seq mod 7)
Pointer to second tier data structure
2nd tier (128 entries) Pointer to head of fragment Frag chunk 0 Frag chunk 1 Frag chunk 2 Frag chunk N
The incoming sequence number is compared with the expected sequence number (head + 1). If the two are equal, the datagram is in sequence. The end of packet marker is examined to determine if a complete frame/packet is available for transfer. This is signaled to the frame builder block. A session that was previously out-of-sequence may have a backlog of frames/packets ready for transfer once the in-sequence frame/packet is received. This is signaled to the frame assembly block. If the sequence numbers do not align, and the multilink session was previously in sequence, a re-sequencing operation is triggered and the datagram is logically placed in the re-sequencing buffers. The datagram is removed from the re-sequencing buffers when the resequencing operation has correctly re-sequenced the datagrams. These
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datagrams are passed to the frame builder of the ingress queue manager depending on the mode of transfer. Frames/packets without sequence numbers use the same data structures to queue frames. However the re-sequencing and frame detection logic is not required. FRF12 fragmentation (single link sequencing for QOS reasons) and the potential equivalent for PPP are supported via the structures in place. In order to preserve integrity of the data structures in the event of a soft error the addresses are protected by ECC capable of detecting 2 and correcting 1 error. 10.9.5.6 Frame building
Frame or packet transfers across the ANY-PHY interface require all the fragments of a frame/packet to be present and in sequence before the transfer can occur. The frame building block monitors incoming datagrams determines when a complete frame/packet has been received and is ready for transfer. Examining status fields associated with datagrams that are entered in the 14 bitsliding window provides the necessary information. Multilink sessions that are insequence require the end-of-packet marker of incoming packets to be examined. When the frame builder detects the end of packet marker, the CI is sent to the ingress queue manager. This signals that a frame/packet is ready for transfer. Out-of-sequence multilink sessions require the frame builder to rapidly parse the fragment entries in the data structure once the multilink session returns to insequence state. This is required as there may be a large number of fragments that are available for transmission once the session becomes in-sequence (i.e. the outstanding fragment arrives and completes the sequence). To support this, the frame builder maintains a block of status structures. Each block contains 128 status entries. This enables the frame builder to review a large number of fragments once the session is in sequence. If one or more complete frames are identified, the frame builder provides the associated connection identifier to the ingress queue and the number of frames available. 10.9.5.7 Frame/Fragment removal
The connection identifier selected by the ingress queue manager is used to extract the datagram at the head of the connection queue. If this is the last entry in a secondary tier, the re-sequencing data structure is returned to the free list of data structures. When the data is extracted, the corresponding status bits (EOP, Active, BECN, FECN, DE) are cleared. The address field is cleared and a Null pointer is placed in the location.
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10.9.6 Ingress Queue manager (IQM-12) The ingress queue manager (Figure 23) arbitrates between datagrams that are available to be sent. Datagram selection is based on the priority of the respective queue. The intent is to maximize the datagram transfers while ensuring that individual HDLC channels and connections receive adequate access to the ANYPHY interface. It is not desirable to have a burst of traffic from a multilink bundle (due to re-sequencing) dominate the ANY-PHY interface at the expense of other HDLC channels that also have data to send. Figure 23 - The Ingress Queue Manager block
Hi
C I u p d a te
Low
The ingress queue manager supports arbitration between two queues. These are used to support two priorities. Each queue is a linked list of CIs that have data to transmit. When a datagram is formed, the re-sequencing block forwards a CI, to the ingress queue manager. If the CI is not on the list, the CI is added to the end of the linked list. The high priority queue is serviced before the low priority queue. The CI tag at the head of the selected queue is extracted and passed to the resequencing engine. Where it is used to extract the frame/fragment. If the CI has more datagrams to send (size 0) it is placed at the end of the queue. 10.9.7 Receive ANY-PHY Interface (RAPI-12) The RAPI-12 contains a FIFO block for latency control as well as to segregate the APPI timing domain from the SYSCLK timing domain. The RAPI-12 contains the necessary logic to manage and respond to device polling from an upper layer
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device. The RAPI-12 also provides the upper layer device with status information on a per packet basis. The RAPI-12 supports ANY-PHY Level-2, and ANY-PHY Level-3 modes of operation. When operating at 104 MHz the lower 8 bits of the data are active. 10.9.7.1 FIFO Storage and Control
The FIFO block temporarily stores ANY-PHY channel data during transfer across the Rx APPI. A separate storage element samples the 16-bit address prepend to associate the data in that FIFO with a specific ANY-PHY channel. This ANY-PHY channel ID is prepended in-band as the first word of every burst data transfer across the Rx APPI. In ANY-PHY Level-3 mode, the address prepend is appended on the first two bytes of the packet. The writer controller provides a means for writing data into the FIFO. The reader controller provides a means of reading data out of the FIFO onto the Rx APPI. When selected to do so the reader controller will read the data out of the FIFO. To prevent from overloading the Rx APPI with several small bursts of data, the RAPI-12 automatically deselects after every burst transfer. This provides time for the upper layer device to detect an end of packet indication and possibly reselect a different FREEDM-336A1024 device without having to store the extra word or two that may have been output onto the Rx APPI during the time it took for deselection. The RAPI-12 provides packet status information on the Rx APPI at the end of every packet transfer. The RAPI-12 asserts RERR at the end of packet reception (REOP high) to indicate that the packet is in error. The RAPI-12 may optionally be programmed to overwrite RXDATA[7:0] of the final word of each packet transfer (REOP is high) with the status of packet reception when that packet is erred (RERR is high). Overwriting of status information is enabled by setting the STATEN bit in the RAPI-12 control register. 10.9.7.2 Polling Control and Management
The RAPI-12 only responds to ANY-PHY channel polls that match the device base address bits programmed in the RAPI-12 Base Address register. A positive poll response indicates that the FIFO is ready to be selected to transfer this data across the Rx APPI. 10.9.8 Transmit ANY-PHY Interface (TAPI-12) The Transmit ANY-PHY Interface (TAPI-12) provides a low latency path for transferring data from the Transmit ANY-PHY Packet Interface (Tx APPI) to the TFRAG engine or the EQM. The TAPI-12 contains a FIFO block for latency control
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as well as to segregate the APPI timing domain from the SYSCLK timing domain. The TAPI-12 contains the necessary logic to manage and respond to ANY-PHY channel polling from an upper layer device. The TAPI-12 supports ANY-PHY Level-2, and ANY-PHY Level-3 modes of operation FIFO Storage and Control. The FIFO block temporarily stores ANY-PHY channel data during transfer across the Tx APPI. TAPI-12 burst data transfers are transaction based on the writer side of the FIFO. The first word of each burst transfer contains the address prepend field. A separate storage element samples the address prepend to associate the data with a specific ANY-PHY channel. The address prepend is compared to the base and range registers. The address prepend must correspond to an ANY-PHY channel that is supported by the FREEDM-336A1024 for the TAPI-12 to respond to the data transaction on the Tx APPI. The writer controller provides a means for writing data from the Tx APPI into the FIFO. The whisper controller provides the ANY-PHY channel address of the data being written into the FIFO. As soon as the first word of data has been written into the FIFO, the whisper controller provides the ANY-PHY channel information for that data to the downstream block. The whisper controller will wait for acknowledgement and the reader controller is then requested to read the data from the FIFO. Once the reader controller has commenced the data transfer, the whisper controller will provide the ANY-PHY channel information for next data transfer received, if any. The reader controller provides a means of reading data out of the FIFO. When the writer controller indicates that data has been written into the FIFO, the reader controller is permitted to read that data. The reader controller will then wait for a request for data from the downstream block. Because the reader controller reads data out of the FIFO in the order in which they were filled, the TFRAG block will request data for ANY-PHY channels in the order in which they were whispered. 10.9.8.1 Polling Control and Management
The TAPI-12 only responds to poll addresses that are identified by the base and range address registers in the TAPI-12 Control registers. The TAPI-12 maintains a mirror image of the status of each channel FIFO in the EQM-12. The EQM-12 continuously reports the status of the 1024 FIFOs to the TAPI-12 and the TAPI12 updates the mirror image accordingly. At the beginning of every data transfer across the Tx APPI, the TAPI-12 sets the mirror image status of the channel to "full". Only the TAPI-12 can cause the status to be set to "full" and only the EQM-12 can cause the status to be set to "space". In the event that both the
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TAPI-12 and the EQM-12 try to change the mirror image status of a particular channel simultaneously, the TAPI-12 takes precedence. 10.9.9 Transmit Fragmentor (TFRAG) Datagrams are transferred from the upstream device to the FREEDM-336A1024 via the ANY-PHY interface. The transmit fragmentor fragments (if required) the packet, encapsulates the fragments with a sequence number (in multilink or fragmentation situations), assigns the datagram to an HDLC channel and segments the datagram into chunks for storage in the external SDRAM. When supporting a multilink bundle, the address prepend and the connection identifier that is provided on the ANY-PHY interface are used to index the appropriate sequence number and an index to the HDLC channels associated with the multilink bundle. The sequence number and additional header bits (B, E, and COS) are appended to arriving datagrams. The datagram is assigned to an HDLC channel in the multilink bundle. HDLC channel assignment is based on the current occupancy of the HDLC channels in a multilink bundle. The datagram is assigned to the HDLC channel with the lowest number of bytes in the channel queue. Compressed PPP headers are detected by the TFRAG. The TFRAG is capable of appending sequence numbers onto multilink packets with compressed headers. On a per HDLC channel basis these datagrams are segmented into chunks and are stored in an external SDRAM memory. A HDLC chunk will only consist of data from one packet/frame. Segmented data is encapsulated (Figure 24) to form a 36 byte storage element. The encapsulation contains the next address pointer, the size and a local integrity check that covers the address field. The next address pointer is used to create a linked list of chunks that comprise a datagram. The address indicates where the next chunk of the datagram is located in the external memory. This effectively links the chunks of a datagram in external memory. In the last data chunk, the next address is used to link to the start of the next datagram. The size field is used to indicate how many of the data bytes are actually valid, as the last chunk may not be completely full. The abort is used to trigger an HDLC abort. If a parity error occurred during an ANY-PHY transfer or if the upstream device asserts the TERR signal, the abort is set. The encapsulated data chunk, and an address pointer are passed to the DRAMC controller for storage in external SDRAM. The address pointer is contained in the HDLC channel record and points to the memory location that is placed in the next address pointer field of the previous data chunk for a given datagram. The
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initial chunk of a datagram is stored at an address location, (starting address of the datagram). An address cache is used to hold addresses that can be used for next pointer values. When a chunk is encapsulated, the HDLC channel record will fetch, from the local cache, another address that can serve as the next address for the following data chunk in the datagram. The cache needs to be replenished; this is achieved by requesting, from the DRAMC, a set of new addresses after a threshold in the Cache has been crossed. In order to preserve the address pointers in the presence of soft errors an ECC code is used to detect 2 errors and correct 1 error. Figure 24 - Encapsulated Chunk Structure
a) Encapsulated Chunk Structure (Full = True) Byte 1 Byte 0 ECC(8) L F A 00 NXT_CHUNK_PTR(19) Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 13 Byte 12 Byte 11 Byte 10 Byte 9 Byte 8 Byte 19 Byte 18 Byte 17 Byte 16 Byte 15 Byte 14 Byte 25 Byte 24 Byte 23 Byte 22 Byte 21 Byte 20 Byte 31 Byte 30 Byte 29 Byte 28 Byte 27 Byte 26 b) Encapsulated Chunk Structure (Full = False) Byte 0 Size ECC(8) L F A 00 NXT_CHUNK_PTR(19) Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 12 Byte 11 Byte 10 Byte 9 Byte 8 Byte 7 Byte 18 Byte 17 Byte 16 Byte 15 Byte 14 Byte 13 Byte 24 Byte 23 Byte 22 Byte 21 Byte 20 Byte 19 Byte 30 Byte 29 Byte 28 Byte 27 Byte 26 Byte 25
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Figure 25
- Linked list data structure of a Datagram
Starting Address
Address of 1st chunk in Datagram (stored on a per HDLC channel basis)
Next address pointer Last = False; Full = True
1st chunk in Datagram
Next address pointer Last = False; Full = True
2nd chunk in Datagram
Next address pointer Last = True; Full = False Size = 3
Last chunk in Datagram
10.9.9.1
Egress Queue Manager (EQM-12)
Managing the ANY-PHY channel status, pushing the status to the TAPI-12, accepting transfer requests from the partial packet processor and arbitrating between the requests are the key tasks of the egress queue manager. Segmented datagrams are placed into external memory by the TFRAG block. The number of data bytes in the chunk is added to the ANY-PHY channel size counter. The size is compared against a threshold. An ANY-PHY channel size that exceeds the threshold will cause the EQM-12 to push a status message to the TAPI-12 indicating the ANY-PHY channel is full and will not be accepting any more frames. The EQM-12 maintains the status of all 1024 ANY-PHY channels including the 168 multilink bundles and the 1024 HDLC channels.
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The partial packet processor requests chunks, as memory becomes available. The egress queue manager determines the address of the chunk to be transferred to the partial packet processor. The EQM-12 updates the HDLC and ANY-PHY channel context status and pushes the status of the ANY-PHY channel to the TAPI-12. ANY-PHY channel status is determined by comparing the size of the ANY-PHY channel to the ANY-PHY channel threshold. The two level feedback mechanism is used to avoid starvation of the HDLC channels. The thresholds are programmable and support a number of different bandwidths (DS0, nxDS0, T1, E1, nxT1, nxE1, DS3) and ensure that starvation is avoided. 10.9.10 CB_DRAMC
The CB_DRAMC controls access to/from the Chunk Buffer SDRAM interface present on FREEDM-336A1024. The external SDRAMS provide buffer storage for chunks and addresses pointing to the chunks. The CB_DRAMC block supports a 48 bit wide SDRAM interface operating at 100 MHz. Refresh, bank switching, providing precharge and bus management are functions that reside in the CB_DRAMC. Figure 26 shows the configuration for the external SDRAMs that comprise the Chunk Buffer. 10.9.11 RS_DRAMC
The RS_DRAMC controls access to/from the Re-sequencing SDRAM interface present on FREEDM-336A1024. The external SDRAMS provide CI lookup information as well as pointers used in the resequencing operation. The RS_DRAMC block supports a 32 bit wide SDRAM interface operating at 100 MHz. Refresh, bank switching, providing precharge and bus management are functions that reside in the RS_DRAMC. Figure 27 shows the configuration for the external SDRAMs that comprise the Re-Sequencing buffer.
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Figure 26
- DRAM configuration for the Chunk Buffer Interface
SDRAM A 256 Mbit
CBCSB CBRASB CBCASB CBWEB CBBS[1:0] CBADD[12:0] CBDAT[15:0]
"1" FREEDM336A1024
CKE SYSCLK
CBCSB CBRASB CBCASB CBWEB CBBS[1:0] CBADD[12:0] CBDAT[47:0] SYSCLK
CBCSB CBRASB CBCASB CBWEB CBBS[1:0] CBADD[12:0] CBDAT[15:0]
SDRAM B 256 Mbit
"1"
CKE SYSCLK
CBCSB SDRAM C CBRASB 256 Mbit CBCASB CBWEB CBBS[1:0] CBADD[12:0] CBDAT[15:0]
"1" SYSCLK (100 MHz)
CKE SYSCLK
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Figure 27
- DRAM configuration for the Re-Sequencing Memory Interface
SDRAM A 256 Mbit
RSCSB RSRASB RSCASB RSWEB RSBS[1:0] RSADD[12:0] RSDAT[15:0]
"1" FREEDM336A1024
RSCSB RSRASB RSCASB RSWEB RSBS[1:0] RSADD[12:0] RSDAT[31:0] SYSCLK
CKE SYSCLK
RSCSB RSRASB RSCASB RSWEB RSBS[1:0] RSADD[12:0] RSDAT[15:0]
SDRAM B 256 Mbit
"1"
CKE SYSCLK
SYSCLK (100 MHz)
10.9.12
SRAMC
The external context memory holds data that needs to be accessed by a number of internal blocks. The role of the SRAMC block is to arbitrate these accesses. The Connection context memory supports the frame building block, TFRAG, and IQM-12. The SRAMC supports glueless access to 1, 2 or 4 banks of Pipelined ZBT1 compatible or Standard SRAM. When FREEDM-336A1024 is configured to interface to Standard or ZBT-compatible SSRAM, CCBSELB is the inverse of CCADD[16]. CCBSELB and CCADD[16:17] are used to select 4 banks when 64Kx36 devices are used (see Figure 28). It should be noted that maximum
1
The ZBT-compatible SRAM family includes O ZBT, short for Zero Bus Turnaround, manufactured by IDT, Micron and Motorola, O NoBL, short for No Bus Latency, manufactured by Cypress, and O Nt , short for No turnaround, manufactured by Samsung
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performance is achieved with ZBT SSRAMs. Standard SSRAMs will degrade chip performance by approximately 20%. Figure 28 - 4 Bank Configuration for 8 MB of ZBT or Standard SSRAM
Clock source
CCSELB CCWEB CCADD[15:0] Addr/Ctrl CCDAT[35:0] Data[35:0] 64Kx36 CLK CE2# CE2 CCADD[16] CCBSEL[0] CCADD[17] Addr/Ctrl Data[35:0] 64Kx36 CLK CE2# CE2
Addr/Ctrl Data[35:0] 64Kx36 CLK CE2# CE2
Addr/Ctrl Data[35:0] 64Kx36 CLK CE2# CE2
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Figure 29 - 2 Banks Configuration for 8 M bits of ZBT-compatible or Standard SSRAM
Clock source
CCSELB CCWEB CCADD[16:0] CCDAT[35:0] Addr/Ctrl Data[35:0] Addr/Ctrl Data[35:0]
128Kx36
CLK CE2# CE2 CCADD[17]
128Kx36
CLK CE2# CE2
1
0
Clock source
CCSELB CCWEB CCADD[16:0] CCDAT[17:0] Addr/Ctrl Data[17:0] Addr/Ctrl Data[17:0]
128Kx18
CLK CE2# CE2 CCSELB CCWEB CCADD[16:0] CCDAT[35:18] Addr/Ctrl Data[17:0]
128Kx18
CLK CE2# CE2
Addr/Ctrl Data[17:0]
128Kx18
CLK CE2# CE2
128Kx18
CLK CE2# CE2
1
CCADD[17]
0
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Figure 30
- 1 Bank Configuration for 8 M bits of ZBT or Standard SSRAM
CCSELB CCWEB CCADD[17:0]
Clock source
CCDAT[35:0]
Addr/Ctrl Data[35:0]
256Kx36
CLK
Clock source
CCSELB CCWEB CCADD[17:0] CCDAT[17:0] Addr/Ctrl Data[17:0]
256Kx18
CLK CCSELB CCWEB CCADD[17:0] CCDAT[35:18] Addr/Ctrl Data[17:0]
256Kx18
CLK
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10.9.13
Transmit HDLC Processor (THDL-12)
The HDLC processor is a time-slice state machine that can process up to 1024 independent HDLC channels. The state vector and provisioning information for each HDLC channel is stored in a RAM. Whenever the TCAS-12 requests data, the appropriate state vector is read from the RAM, processed and finally written back to the RAM. The HDLC state-machine can be configured to perform flag insertion, bit stuffing and CRC generation. The HDLC processor requests data from the partial packet processor whenever a request for HDLC channel data arrives. However, the HDLC processor does not start transmitting a packet until the entire packet is stored in the HDLC channel FIFO or until the FIFO free space is less than the software programmable limit. If an HDLC channel FIFO under-runs, the HDLC processor aborts the packet, and generates an interrupt. The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle inserted by the TCAS-12 block. Writing new provisioning data to an HDLC channel resets the channel's entire state vector. 10.9.13.1 Transmit Partial Packet Buffer Processor
The partial packet buffer processor controls the 64 Kbyte partial packet RAM, which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular HDLC channel FIFO buffers. Thus, noncontiguous sections of RAM can be allocated in the partial packet buffer RAM to create an HDLC channel FIFO. Figure 31 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte HDLC channel FIFO. The three pointer values would be written sequentially using indirect block write accesses. When an HDLC channel is provisioned within this FIFO, the state machine can be initialized to point to any one of the three blocks.
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Figure 31
- Partial Packet Buffer Structure Partial Packet Buffer RAM Block Pointer RAM
Block 0 Block 1 Block 2 Block 3 XX 0x03 XX 0xC8
Block 0 Block 1 Block 2 Block 3
16 bytes 16 bytes 16 bytes 16 bytes
Block 200
16 bytes
Block 200
0x01
Block 4095
16 bytes
Block 4095
XX
The partial packet buffer processor is divided into three sections: reader, writer and roamer. The roamer is a time-sliced state machine that tracks each HDLC channel's FIFO buffer free space and signals the writer to service a particular channel. The writer requests data from the EQM-12 block and transfers packet data from the EQM-12 to the associated HDLC channel FIFO. The reader is a time-sliced state machine that transfers the HDLC information from an HDLC channel FIFO to the HDLC processor in response to a request from the HDLC processor. If a buffer under-run occurs for an HDLC channel, the reader informs the HDLC processor and purges the rest of the packet. If a buffer overflow occurs for an HDLC channel (this can only happen if EQM-12 disregards the requests), the THDL-12 overwrites the FIFO contents resulting in data corruption on that particular HDLC channel. When an underflow or an overflow occurs, an interrupt is generated and the cause of the interrupt may be read via the interrupt status register using the microprocessor interface. The writer and reader determine empty and full FIFO conditions using flags. Each block in the partial packet buffer has an associated flag. The writer sets the flag after the block is written and the reader clears the flag after the block is
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read. The flags are initialized (cleared) when the block pointers are written using indirect block writes. The reader declares an HDLC channel FIFO under-run whenever it tries to read data from a block without a set flag. The FIFO algorithm of the partial packet buffer processor is based on per- HDLC channel software programmable transfer size and free space trigger level. Instead of tracking the number of full blocks in an HDLC channel FIFO, the processor tracks the number of empty blocks, called free space, as well as the number of end of packets stored in the FIFO. Recording the number of empty blocks instead of the number of full blocks reduces the amount of information the roamer must store in its state RAM. The partial packet roamer records the FIFO free space and end-of-packet count for all HDLC channel FIFOs. When the reader signals that a block has been read, the roamer increments the FIFO free space and sets a per- HDLC channel request flag if the free space is greater than the hungry or starving threshold. The roamer pushes this status information to the EQM to indicate that it can accept at least one transfer of data. The roamer also decrements the end-ofpacket count when the reader signals that it has passed an end of a packet to the HDLC processor. The roamer listens to control information from the EQM-12 to decide which HDLC channel FIFO requests data from the EQM block. The roamer informs the partial packet writer of the HDLC channel FIFO to process and the FIFO free space. The writer sends a request for data to the EQM-12 block, writes the response data to the HDLC channel FIFO, and sets the block full flags. The writer reports back to the roamer the number of blocks and endof-packets transferred. The maximum amount of data transferred during one request is set by XFER. The roamer round-robins between all HDLC channels FIFOs and pushes the status to the EQM-12 block. The status consists of two pieces of information: (1) is there space in the HDLC channel FIFO for at least 32 bytes of data, and (2) is this channel FIFO at risk of underflowing. The configuration of the HDLC processor is accessed using indirect channel read and write operations as well as indirect block read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle identified by the TCAS-12 block. Writing new provisioning data to an HDLC channel resets the entire state vector. Due to the hard limit of blocks in the partial packet buffer, there are certain combinations of channel bandwidths that cannot be supported. In order to avoid underflows in the partial packet FIFO's, the following rules must be adhered to.
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10.9.13.1.1 Formula For Single Data Rate Table 12 Term XFER[3:0] - Definitions Definition Number of blocks, less one, requested from THDL-12 to EQM-12 in a data transfer. It is defined in THDL Indirect Channel Data #3. Note that (XFER + 1) must be an even number. Total line rate in bits/second. It is the aggregate data rate of all configured HDLC channels. System clock period in unit second. Typically it is equal to 10ns for a system clock frequency of 100 MHz. 55. This is the worst case latency from THDL-12 to EQM-12.
lineRate period latency
Assuming that all channels have the same data rate. To avoid underflow, we must have:
lineRate * (4 * XFER + 4 + latency ) * period < 128( XFER[3 : 0] + 1)
Below is a sample configuration for a single data rate where all 1024 THDL-12 channels have the same data rate. There are a total of 4096 blocks in THDL-12, With 16 bytes of buffer space per block, so each channel will have 4096/1024 = 4 blocks. That is, 4 blocks are used to construct a channel FIFO. The start transmission level is set to 2 blocks. As it is required that XFER[3:0] be less than or equal to start transmission level, we have (XFER+1) <= 2. In order to maximize bandwidth usage, (XFER+1) = 2 is chosen. Note that the EQM-12 can only transfer even number of blocks in a data transfer, so (XFER+1) must always be even. From the above formula, we need lineRate < 406 Mb/s. As a result, each channel will have a data rate < 406/1024 = 0.396 Mb/s. In this application, valid channel rates are multiple DS0 channels, so the maximum channel rate is equal to 6 DS0 channels, i.e., one quarter of T1 rate. In applications where a mixture of T1, E1, DS3 channels are required, that is, channels have different data rate, each channel has to reserve enough channel FIFO space in order to deliver the desired data rate besides avoiding underflow. This is because the channel FIFO is used to handle burst transfers from the EQM-12. A small channel FIFO will limit the burst rate from the EQM-12, thus the bandwidth from EQM-12 to THDL-12 for the particular channel. To calculate the configuration for a particular channel in a mixed format, we first assume that the
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whole lineside bandwidth is allocated to channels with the same data rate as this channel, and then apply the above formula for single data rate. In essence, each data rate in a mixed format will be configured the same way as a corresponding single rate scenario to guarantee that it receive enough bandwidth from the EQM-12. For example, a T1 channel in a mixed format has to reserve enough channel FIFO space to deliver T1 data rate. To find out how to configure this T1 channel, note that a total of 336 T1 channels can be supported by FREEDM336. By assuming all channels are T1 and applying the above formula for single data rate, we get the configuration shown in the following table. Suggested configurations for E1, DS3, and fractional T1 channels are also shown. Table 13 Type 1~6 DS0 7~8 DS0 9 DS0 10~12 DS0 13~23 DS0 1~6 E1 TS 7~9 E1 TS 10 E1 TS 11~16 E1 TS 17~31 E1 TS T1 E1 DS3 - THDL Configuration for Single Data Rate Channels FLEN 3 5 5 7 11 3 5 7 7 15 11 15 335 Level Trans XFER[3:0] 0010 0010 0010 0100 0100 0010 0010 0100 0100 0101 0100 0101 1100 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 1 1 3 3 5 3 5 15 Inhibit Starving 1 1 1 1 x 1 1 1 1 x x x x Max. Channels 1024 682 672 512 336 1024 682 512 504 252 336 252 12
Note: In addition, (FLEN+1) >= (XFER[3:0]+1) Inhibit of x means it could be 0 or 1 depending on exact configuration.
10.9.14
Transmit Channel Assignor (TCAS-12)
The Transmit Channel Assignor block (TCAS-12) processes up to 1024 HDLC channels. Data for all HDLC channels is sourced from a single byte-serial stream from the Transmit HDLC Controller / Partial Packet Buffer block (THDL-12). The TCAS-12 demultiplexes the data and assigns each byte to any one of 336 links. When sending data to the SBI block, each link may be configured to support channelized T1/J1/E1 traffic, unchannelized DS3 traffic or unframed traffic at T1/J1, E1, DS3 or Fractional DS3 rates. When sending data to the TD outputs,
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links 0, 1 through 11 support unchannelized data at arbitrary rates up to 52 Mbps. Each link is independent and has its own associated clock. The 336 TCAS links have a fixed relationship to the SPE and tributary numbers on the SBI ADD BUS as shown in the following table. Table 14 SBISPE No. 1-1 1-2 1-3 1-1 1-2 1-3 1-1 1-2 1-3 l l l 1-1 1-2 1-3 28 28 28 324 328 332 2-1 2-2 2-3 SBI Trib. No. 1 1 1 2 2 2 3 3 3 TCAS Link No. 0 4 8 12 16 20 24 28 32 - SBI-SPE Tributary to TCAS Link Mapping SBISPE No. 2-1 2-2 2-3 2-1 2-2 2-3 2-1 2-2 2-3 SBI Trib. No. 1 1 1 2 2 2 3 3 3 l l l 28 28 28 325 329 333 3-1 3-2 3-3 TCAS Link No. 1 5 9 13 17 21 25 29 33 SBISPE No. 3-1 3-2 3-3 3-1 3-2 3-3 3-1 3-2 3-3 SBI Trib. No. 1 1 1 2 2 2 3 3 3 l l l 28 28 28 326 330 334 4-1 4-2 4-3 28 28 28 TCAS Link No. 2 6 10 14 18 22 26 30 34 SBISPE No. 4-1 4-2 4-3 4-1 4-2 4-3 4-1 4-2 4-3 SBI Trib. No. 1 1 1 2 2 2 3 3 3 TCAS Link No. 3 7 11 15 19 23 27 31 35 l l l 327 331 335
As shown in the table above, TCAS links 0, 1, through 11 are mapped to tributary 1 of SBI/SPEs 1, 2 through 11 respectively. These links may be configured to operate at DS3 rate. (They may also be configured to output data to the TD outputs at rates up to 52 Mbps.) For each of these high-speed links, the TCAS12 provides a 4 byte FIFO. For the remaining links (TCAS links 12 to 335 mapped to tributaries 2 to 28 of each SPE), the TCAS-12 provides a single byte holding register. In the event where multiple links are in need of data, TCAS-12
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requests data from upstream blocks on a fixed priority basis with link 0 having the highest priority and link 335 the lowest. It should be noted that for every SBI/SPE used as a serial link, the SBI/SPE must be disabled on the SBI Bus interface and visa versa. Links containing a T1/J1 or an E1 stream may be channelized. Data at each time-slot can be independently assigned to be sourced from a different HDLC channel. The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse. With knowledge of the transmit link and time-slot identity, the TCAS-12 performs a table look-up to identify the HDLC channel from which a data byte is to be sourced. Links containing a DS3 stream are unchannelized; in which case, all data bytes on the link belong to one HDLC channel. The TCAS-12 performs a table look-up to identify the HDLC channel to which a data byte belongs using only the outgoing link identity, as no time-slots are associated with unchannelized links. Links may additionally be configured to operate in an unframed "clear channel" mode, in which case the FREEDM-336A1024 will output HDLC data in all bit positions, including those normally reserved for framing information. Links so configured operate as unchannelized regardless of link rate and the TCAS-12 performs a table lookup using only the link number to determine the associated HDLC channel. 10.9.15 SBI Inserter
The SBI transmit circuitry processes data for the twelve Synchronous Payload Envelopes (SPEs) conveyed on the SBI ADD BUS. It receives data bytes from the transmit channel assignor and inserts it into the SBI ADD BUS. The SBI Insert block may be configured to enable or disable transmission of individual tributaries on to the SBI ADD bus. Individual tributaries may also be configured to operate in framed or unframed mode. 10.9.16 Performance Monitor
The Performance Monitor block (PM) contains the HDLC channel counters plus a series of error registers. The HDLC channel counters include: * * * * Bytes received per HDLC channel Bytes transmitted per HDLC channel Total datagrams received Total datagrams transmitted
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* *
Bytes discarded from excess small datagrams Bytes discarded of Chunk Buffer allocation exceeded events
In addition a number of error conditions are tracked on a per HDLC channel basis: * * * * * Erred HDLC Frames Tx HDLC framing aborts Rx HDLC framing aborts Small Datagrams discarded events Chunk Buffer allocation exceeded events
Additionally, the PM-12 block contains global error counters track performance of various aspects of the FREEDM-336A1024.These include: * * * * * * * * * * * * * Number of lost fragment events. Partial Packet overruns Partial Packet underruns Number of tiny Packets (min HDLC length) Number of excessive fragments per packet/frame events Number of unexpected sequence number events Number of bytes received with non-octet aligned errors Number of bytes received with MRU exceeded Number of bytes received with abort errors Number of bytes received with FCS errors Number of bytes received with partial packet overrun Number of bytes received with unexpected sequence number Number of bytes received with unsupported header format
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10.9.17
Digital Delay Lock Loop (DDLL)
The DLL is used to minimize output delay on all external RAMs. The DLL measures the phase difference between the external clock and a reference clock and generates an internal clock, which reduces the phase difference between the external clock and the reference clock to zero. 10.9.18 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The FREEDM-336A1024 identification code is 073880CD hexadecimal. 10.9.19 Microprocessor Interface
The FREEDM-336A1024 supports microprocessor access to an internal register space for configuring and monitoring the device. All registers are on 32 bit boundaries. Address Bit 12 on all registers must be set to 0. The registers are described in Table 15. Table 15 Map Address 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020-0x044 0x048 0x04C 0x050-0x064 - Normal Mode Microprocessor Accessible Registers Memory Register F336 Master Reset and Control F336 Master High Priority Interrupt Enable F336 Master High Priority Interrupt Status F336 Master Clock / Frame Pulse Activity Monitor and Accumulation Trigger F336 Reserved F336 Master Line Loopback F336 Master Low Priority Interrupt Enable F336 Master Low Priority Interrupt Status F336 Reserved F336 SBI DROP BUS Master Configuration F336 SBI ADD BUS Master Configuration F336 Reserved
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Address 0x068 0x06C 0x070 0x074 0x078 - 0x0FC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 - 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 - 0x21C 0x220 0x224 0x228 - 0x23C 0x240 - 0x37C 0x380 0x384 0x388 0x38C 0x390
Register DLL Configuration DLL Vernier Control DLL Delay Tap Status DLL Control Status DLL Reserved RCAS Indirect Context RAM Link Select RCAS Indirect Context RAM Link Data RCAS Indirect Channel Provision RAM TRIB Select RCAS Indirect Channel Provision RAM Time Slot and control Select RCAS Indirect Channel Provision RAM Channel Data and Loopback enable. RCAS Serial Link Select RCAS Reserved RHDL Indirect Channel Select RHDL Indirect Channel Data Register #1 RHDL Indirect Channel Data Register #2 RHDL Reserved RHDL Indirect Block Select RHDL Indirect Block Data Register RHDL Reserved RHDL Configuration RHDL Maximum Packet Length RHDL Reserved RHDL Reserved THDL Indirect Channel Select THDL Indirect Channel Data #1 THDL Indirect Channel Data #2 THDL Indirect Channel Data #3 THDL Indirect Channel Data Register #4
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Address 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 - 0x3AC 0x3B0 0x3B4 - 0x3BC 0x3C0 - 0x3FC 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C - 0x508 0x50C - 0x57C 0x580 0x584 0x588 0x58C 0x590 - 0x5BC 0x5C0 0x5C4 - 0x5CC 0x5D0 0x5D4 0x5D8
Register THDL Indirect Channel Data Register #5 THDL Indirect Channel Data Register #6 THDL Reserved THDL Indirect Block Select THDL Indirect Block Data THDL Reserved THDL Configuration THDL Reserved THDL Reserved TCAS Indirect Context RAM Link Select TCAS Indirect Context RAM Link Data TCAS Indirect Channel Provision RAM TRIB Select TCAS Indirect Channel Provision RAM Timeslot and Control Select. TCAS Indirect Channel Provision RAM Channel Data TCAS Serial Link Select TCAS Idle Time-slot Fill Data TCAS Reserved TCAS Reserved RAPI Control Register RAPI Device Base Address Register RAPI Channel Base Address Register RAPI Status Register RAPI Reserved SBI EXTRACT Control SBI EXTRACT Reserved SBI Reserved SBI EXTRACT Tributary Indirect Access Address SBI EXTRACT Reserved
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Address 0x5DC 0x5E0 0x5E4 0x5E8 0x5EC 0x5F0 - 0x5FC 0x600 0x604 0x608 0x60C 0x610 0x614 0x618 0x61C - 0x63C 0x640 - 0x67C 0x680 0x684 - 0x688 0x68C 0x690 0x694 0x698 0x69C 0x6A0 0x6A4 0x6A8 0x6AC 0x6B0 - 0x7FC 0x800 0x804 - 0x810
Register SBI EXTRACT Tributary Indirect Access Data SBI EXTRACT SBI1 SPE Configuration Register SBI EXTRACT SBI2 SPE Configuration Register SBI EXTRACT SBI3 SPE Configuration Register SBI EXTRACT SBI4 SPE Configuration Register SBI EXTRACT Reserved TAPI Control TAPI Indirect Channel Provisioning TAPI Indirect Channel Data Register TAPI Reserved Register TAPI Status Register TAPI Base Address Register TAPI Range Address Register TAPI Reserved TAPI Reserved SBI INSERT Control SBI INSERT Reserved SBI INSERT T1 Frame Pulse Offset SBI INSERT E1 Frame Pulse Offset SBI INSERT Tributary Indirect Access Address SBI INSERT Reserved SBI INSERT Tributary Indirect Access Data SBI INSERT SBI1 SPE Configuration Register SBI INSERT SBI2 SPE Configuration Register SBI INSERT SBI3 SPE Configuration Register SBI INSERT SBI4 SPE Configuration Register SBI INSERT Reserved Memory Port Control Memory Write Data (Burstable)
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Address 0x814-0x818 0x81C-0x828 0x82C-0x830 0x834-0x880 0x884 0x888 0x88C 0x890 0x894-0x8FC 0x900 0x904 0x908 0x90C-0x914 0x918 0x91C 0x920 0x924-0x99C 0x9A0 0x9A4 0x8A8 0x9AC 0x9B0 0x9B4 0x9B8 0x9BC 0x9C0 0x9C4 0x9C8 0x9CC
Register Memory Write Data Overflow (Burstable) Memory Read Data (Burstable) Memory Read Data Overflow (Burstable) BUMP Reserved Unexpected SN Register CI (USNCI) Lost SN CI (LSNCI) SRAM Parity Error Address (SPERRADD) Excessive number of Fragments CI (ENFCI) BUMP Reserved CB_DRAMC Status Register CB_DRAMC_COECCE Register CB_DRAMC_UNCOECCE Register CB_DRAMC Reserved RS_DRAMC Status Register RS_DRAMC_COECCE Register RS_DRAMC_UNCOECCE Register DRAM Reserved BIST Controller BIST Enable BIST Result BIST End EXSBI336 BIST ERROR INSBI336 BIST ERROR RCAS-12 BIST ERROR TCAS-12 BIST ERROR RHDL-12 BIST ERROR THDL-12 BIST ERROR PM-12 BIST ERROR RFRAG BIST ERROR
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Address 0x9D0 0x9D4 0x9D8 0x9DC 0x9E0 0x9E4 0x9E8 0x9EC 0x9F0-0xEFF
Register TFRAG BIST ERROR RS_DRAMC BIST ERROR CB_DRAMC BIST ERROR IQM-12 BIST ERROR EQM-12 BIST ERROR FRMBLD BIST ERROR RAPI-12 BIST ERROR TAPI-12 BIST ERROR Unused
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11 NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the FREEDM-336A1024. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. Except where noted, all configuration bits that can be written into can also be read back. This allows the processor controlling the FREEDM-336A1024 to determine the programming state of the block. 3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect FREEDM-336A1024 operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the FREEDM336A1024 operates as intended, reserved register bits must only be written with their default values or defined setup values. Similarly, writing to reserved registers should be avoided. 6. The term "high" may be used to describe logic 1 and "low" may be used to describe logic 0. 11.1 Microprocessor Accessible Registers For each register description below, the hexadecimal register number indicates the address in the FREEDM-336A1024 when accesses are made using the external microprocessor. Note These 32-bit registers are not byte addressable. Writing to any one of these registers modifies all bits in the register.
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Register 0x000 : F336 Master Reset and Control Bit Bit 31 To Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R R R R R R R R R R R R RESET SRAMM1 SRAMM0 DTYPE[3] DTYPE[2] DTYPE[1] DTYPE[0] ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 Type Function Unused Default X
This register provides software reset capability, device ID information and SRAM configuration setup. RESET: The RESET bit allows the FREEDM-336A1024 to be reset under software control. If the RESET bit is a logic one, the entire FREEDM-336A1024, except the microprocessor interface, is held in reset. All registers are reset to their default values and some memories are set to their default values (for specific memory operation refer to memory descriptions). This bit is not self-clearing. Therefore, a logic zero must be written to bring the FREEDM336A1024 out of reset. Holding the FREEDM-336A1024 in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset.
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Note: Unlike the hardware reset input (RSTB), RESET does not force the FREEDM336A1024's microprocessor interface pins tristate. RESET causes all registers to be set to their default values and forces the APPI outputs tristate. SRAMM[1:0]: The SRAM Mode bits describe the choice of SSRAM used for the Connection Context (CC) external memory. Table 16 - Memory mode Configuration SRAMM[1:0] 00 01 10 11 DTYPE[3:0]: The Device Type bits (DTYPE[3:0]) allow software to identify the device as the FREEDM-336A1024 member of the FREEDM family of products. ID[7:0]: The Device ID bits (ID[7:0]) allow software to identify the version level of the FREEDM-336A1024. Configuration Standard SRAM Reserved ZBT-like SRAM Reserved
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Register 0x004 : FREEDM-336A1024 Master High Priority Interrupt Enable Bit Bit 31 To Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SBIC1FPSE SDGMDE CBAEXE Reserved Reserved UNSUPHE BADSIZEE RSFPPEE EFPPEE IFPPEE DLLE SBIPARI TXCHQOVRE CFOVRE TPRTYE TFOVRE TFUDRE SRAMPE UECCRSE UECCCBE RFOVRE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register provides interrupt enables for various events detected or initiated by the FREEDM-336A1024. Each interrupt enable bit corresponds to the equivalent bit in the Master High Priority Interrupt Status register. All interrupt enable bits are active high. When high, interrupts are enabled. When low, interrupts are masked. While interrupts are masked the status bit in the status register may still be
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polled to detect the error event. Enabled High priority interrupts cause the INTHIB interrupt pin to be asserted. Reserved: The Reserved bits must be set to 0 for correct operation of the FREEDM336A1024 device.
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Register 0x008 : F336 Master High Priority Interrupt Status Bit Bit 31 To Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
SBIC1FPSI SDGMDI CBAEXI Reserved RST_DONEI UNSUPHFI BADSIZEI RSFPPEI EFPPEI IFPPEI DLLI SBIPARI TXCHQOVRI CFOVRI TPRTYI TFOVRI TFUDRI SRAMPI UECCRSI UECCCBI RFOVRI
X 0 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register reports the high priority interrupt status for various events detected or initiated by the FREEDM-336A1024. Reading this register acknowledges and
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clears the interrupts. The register is also writeable to allow s/w testing of interrupt generation and service routines. RFOVRI: The receive Partial Packet FIFO overrun error interrupt status bit reports receive Partial Packet FIFO overrun error interrupts to the microprocessor. RFOVRI is set high on attempts to write data into the logical FIFO of a channel when it is already full. RFOVRI remains valid when interrupts are disabled and may be polled to detect receive FIFO overrun events. UECCCBI: The Uncorrected ECC Error detected on Chunk Buffer Memory interrupt status bit reports such an event to the microprocessor. UECCCBI is set high when an ECC Error that could not be corrected is detected during a memory access to the Chunk Buffer Memory. When set, the CB_DRAMC_UNCOECCE Register will hold the last DRAM address that was being accessed when an ECC Error occurred. UECCCBI and CB_DRAMC_UNCOECCE remain valid when interrupts are disabled and may be polled to detect error events. UECCRSI: The Uncorrected ECC Error detected on Re-sequencing Memory interrupt status bit reports such an event to the microprocessor. UECCRSI is set high when an ECC Error that could not be corrected is detected during a memory access to the Re-sequencing Memory. When set, the RS_DRAMC_UNCOECCE Register will hold the last DRAM address that was being accessed when an ECC Error occurred. UECCRSI and RS_DRAMC_UNCOECCE remain valid when interrupts are disabled and may be polled to detect error events. SRAMPI: SRAM Parity Error interrupt status bit reports parity error interrupts to the microprocessor. SRAMPI is set high whenever a parity error is detected on accesses to external SRAM. When set, the SRAM Parity Error Address (SPERRADD) Register will hold the last SRAM address that was being accessed when a parity error occurred. SRAMPI and SPERRADD remain valid when interrupts are disabled and may be polled to detect error events.
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TFUDRI: The transmit Partial Packet FIFO underflow error interrupt status bit reports transmit Partial Packet FIFO underflow error interrupts to the microprocessor. TFUDRI is set high upon attempts to read data from the logical FIFO when it is already empty. TFUDRI remains valid when interrupts are disabled and may be polled to detect transmit FIFO underflow events. TFOVRI The transmit Partial Packet FIFO overflow error interrupt status bit reports transmit Partial Packet FIFO overflow error interrupts to the microprocessor. TFOVRI is set high upon attempts to write data to the logical FIFO when it is already full. TFOVRI remains valid when interrupts are disabled and may be polled to detect transmit FIFO overflow events. TPRTYI: The transmit parity error interrupt status bit reports the detection of a parity error on the transmit APPI. TPRTYI is set high upon detection of a parity error. TPRTYI remains valid when interrupts are disabled and may be polled to detect parity errors. CFOVRI: The Circular FIFO Overflow interrupt status bit reports TAPI Circular FIFO overflow error interrupts to the microprocessor. CFOVRI is set high upon attempts to write to the circular FIFO when it is already full. CFOVRI remains valid when interrupts are disabled and may be polled to detect Circular FIFO Overflow events. (NOTE - Circular FIFO overflows will not occur if the TRDY is observed or specified minimum spacing between small packets is adhered.) TXCHQOVRI: The Transmit Channel Queue Overflow interrupt status bit reports EQM-12 Channel Queue overflow error interrupts to the microprocessor. TXCHQOVRI is set high upon attempts to write to the Queue when it is already full. TXCHQOVRI remains valid when interrupts are disabled and may be polled to detect Queue Overflow events. (NOTE - Queue overflows will not occur if Channel availability polling is observed and adhered.) SBIPAR: The SBI Parity interrupt status bit (SBIPARI) reports a parity on the SBI bus. SBIPARI remains valid when interrupts are disabled and may be polled to detect SBI Parity error conditions.
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DLLI: The delay line error event interrupt status bit (DLLI) indicates the DLL ERROR register bit has gone high. When the DLL ERROR register changes from a logic zero to a logic one, the DLLI register bit is set to logic one. DLLI remains valid when interrupts are disabled and may be polled to detect DLL error events. IFPPEI: The Ingress FPP Empty interrupt status bit (IFPPEI) indicates that the Ingress FPP FIFO is empty. IFPPEI is set high upon detection of such this condition. IFPPEI remains valid when interrupts are disabled and may be polled. EFPPEI: The Egress FPP Empty interrupt status bit (EFPPEI) indicates that the Egress FPP FIFO is empty. EFPPEI is set high upon detection of such a condition. EFPPEI remains valid when interrupts are disabled and may be polled. RSFPPEI: The Re-sequencing FPP Empty interrupt status bit (RSFPPEI) indicates that the Re-sequencing Memories FPP FIFO is empty. RSFPPEI is set high upon detection of such a condition. RSFPPEI remains valid when interrupts are disabled and may be polled. BADSIZEI: The Bad Size interrupt status bit (BADSIZEI) indicates that the RAPI-12 block received a segment of incorrect size. If such an interrupt occurs, the ANYPHY specification will be violated. BADSIZEI remains valid when interrupts are disabled and may be polled. Under normal operation, this interrupt will never occur. Assertion of this interrupt should trigger a chip reset. UNSUPHFI The IQM-12 interrupt status bit reports a datagram with an unsupported header format was detected. (In particular, Frame Relay datagrams carrying a 16, 17, or 23 bit DLCI, or PPP datagrams with PID(H) even and/or PID(L) odd). UNSUPHFI remains valid when interrupts are disabled and may be polled. RST_DONEI The RST_DONEI status bit reports the ending of the hardware reset or software reset operation, it indicates that all of the flip-flops and internal RAMs have been initialized. The RST_DONEI cannot be enabled but can be polled to indicate reset completion.
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Reserved: The reserved bit can be set to any value. CBAEXI The Chunk Buffer Allocation Exceeded Interrupt status bit reports chunk buffer allocation exceeded events. CBAEXI remains valid when interrupts are disabled and may be polled. SDGMDI The Small Datagram discard Interrupt status bit reports small datagram discard events due to insufficient bandwidth to sustain the number of small datagrams (less than 40 bytes) received. SDGMDI remains valid when interrupts are disabled and may be polled. SBIC1FPSI The SBIC1FPS Interrupt status bit reports C1FP realignment events on the SBI bus. SBIC1FPSI remains valid when interrupts are disabled and may be polled.
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Register 0x00C : F336 Master Clock / Frame Pulse Activity Monitor Bit Bit 31 To Bit 30 Bit 29 To Bit 18 Bit 17 To Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R TXCLKA RXCLKA DC1FPA AC1FPA REFCLKA SYSCLKA X X X X X X R TCLKA[11:0] X R RCLKA[11:0] X Type Function Unused Default X
This register provides activity monitoring on the FREEDM-336A1024 clock and SBI frame pulse inputs. When a monitored input makes a transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point, all the bits in this register are cleared. The corresponding register bit reading low indicates a lack of transitions. This register should be read periodically to detect stuck at conditions. SYSCLKA: The system clock active bit (SYSCLKA) monitors for low to high transitions on the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is set low when this register is read. REFCLKA: The SBI reference clock active bit (REFCLKA) monitors for low to high transitions on the REFCLK input. REFCLKA is set high on a rising edge of REFCLK, and is set low when this register is read.
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AC1FPA: The SBI Add Bus frame pulse active bit (AC1FPA) monitors for low to high transitions on the AC1FP input. AC1FPA is set high on a rising edge of AC1FP, and is set low when this register is read. DC1FPA: The SBI Drop Bus frame pulse active bit (DC1FPA) monitors for low to high transitions on the DC1FP input. DC1FPA is set high on a rising edge of DC1FP, and is set low when this register is read. RXCLKA: The ANY-PHY receive clock active bit (RXCLKA) monitors for low to high transitions on the RXCLK input. RXCLKA is set high on a rising edge of RXCLK, and is set low when this register is read. TXCLKA: The ANY-PHY transmit clock active bit (TXCLKA) monitors for low to high transitions on the TXCLK input. TXCLKA is set high on a rising edge of TXCLK, and is set low when this register is read. TCLKA[11:0]: The Serial Transmit Clock active bits (TCLKA) monitor for low to high transitions on the TCLKn inputs. TCLKA is set high on a rising edge of TCLK, and is set low when this register is read. RCLKA[11:0]: The Serial Receive Clock active bits (RCLKA) monitor for low to high transitions on the RCLKn inputs. RCLKA is set high on a rising edge of RCLK, and is set low when this register is read.
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Register 0x014 : F336 Master Line Loopback Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LLBEN[11] LLBEN[10] LLBEN[9] LLBEN[8] LLBEN[7] LLBEN[6] LLBEN[5] LLBEN[4] LLBEN[3] LLBEN[2] LLBEN[1] LLBEN[0] 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register controls line loopback for the twelve serial data links. LLBEN[11:0]: The line loopback enable bits (LLBEN[11:0]) control line loopback for links #11 to #0. When LLBEN[n] is set high, the data on RD[n] is passed verbatim to TD[n], which is then updated on the falling edge of RCLK[n]. TCLK[n] is ignored. When LLBEN[n] is set low, TD[n] is processed normally.
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Register 0x018 : F336 Master Low Priority Interrupt Enable Bit Bit 31 To Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UNTSXE TUNPVE CECCRSE CECCCBE RPFEE RABRTE RFCSEE MPISTATE ENFEE USNEE LSNEE 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register provides low priority interrupt enables for various events detected or initiated by the FREEDM-336A1024. Each low priority interrupt enable bit corresponds to the equivalent bit in the Master Low Priority Interrupt Status register. All interrupt enable bits are active high. When high, interrupts are enabled. When low, interrupts are masked. While interrupts are masked the status bit in the status register may still be polled to detect the error event. Enabled low priority interrupts cause the INTLOB interrupt pin to be asserted.
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Register 0x01C : F336 Master Low Priority Interrupt Status Bit Bit 31 To Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UNTSXI TUNPVI CECCRSI CECCCBI RPFEI RABRTI RFCSEI MPISTATI ENFEI USNEI LSNEI 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register reports the interrupt status for various events detected or initiated by the FREEDM-336A1024. Reading these registers acknowledges and clears the interrupts. The register is also writeable to allow s/w testing of interrupt generation and service routines. LSNEI: The Lost Sequence Number Event interrupt status bit indicates a datagram has been declared lost. A datagram is declared lost after a timeout period of 100ms or greater. When set, the Lost SN CI Register (LSNCI) holds the CI number of the last connection to detect a lost SN event. LSNEI and LSNCI remain valid when interrupts are disabled and may be polled to detect lost SN events.
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USNEI: The Unexpected Sequence number interrupt status bit reports unexpected SN conditions to the microprocessor. USNEI is set high when an unexpected SN is detected. When set, the Unexpected SN CI Register (USNCI) holds the CI number of the last connection to detect an unexpected SN. USNEI and USNCI remain valid when interrupts are disabled and may be polled to detect unexpected SN events. ENFEI: The number of Fragments per packet greater than Maximum allowed interrupt status bit reports when a packet with 82 or more fragments has been detected. ENFEI is active high. When set, the Excessive Number of Fragments CI Register (ENFCI) holds the CI number that caused the interrupt. ENFEI and ENFCI remain valid when interrupts are disabled and may be polled. This interrupt is only generated when output format is frame/packet (not in fragment out mode). MPISTATI: When asserted, the Memory Port Idle Status bit indicates to the microprocessor that the memory port has completed its last command. This signal is the inverse of MPBusy found in the Memory Port Control Register. MPISTATI remains valid when interrupts are disabled and may be polled to indicate idle status. RFCSEI: The receive frame check sequence error interrupt status bit reports receive FCS error interrupts to the microprocessor. RFCSEI is set high when a mismatch between the received FCS code and the computed CRC residue is detected. RFCSEI remains valid when interrupts are disabled and may be polled to detect receive FCS error events. Erred datagrams will be redirected during CI lookup and can be programmed to a separate CI. In addition, the RERR bit on the Rx ANY-PHY interface will be set. RABRTI: The receive abort interrupt status bit reports receive HDLC abort interrupts to the microprocessor. RABRTI is set high upon receipt of an abort code (at least 7 contiguous 1's). RABRTI remains valid when interrupts are disabled and may be polled to detect receive abort events. RPFEI: The receive packet format error interrupt status bit reports receive packet format error interrupts to the microprocessor. RPFEI is set high upon receipt
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of a packet that is longer than the maximum programmed length, of a packet that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned. RPFEI remains valid when interrupts are disabled and may be polled to detect receive packet format error events. CECCCBI: The Corrected ECC Error on Chunk Buffer Memory interrupt status bit reports such an event to the microprocessor. CECCCBI is set high when an ECC Error that was corrected is detected during a memory access to the Chunk Buffer Memory. When set, the CB_DRAMC_COECCE Register will hold the DRAM address that was being accessed when the ECC Error occurred. CECCCBI and CB_DRAMC_COECCE remain valid when interrupts are disabled and may be polled to detect error events. CECCRSI: The Corrected ECC Error on Re-sequencing Memory interrupt status bit reports such an event to the microprocessor. CECCRSI is set high when an ECC Error that was corrected is detected during a memory access to the Resequencing Memory. When set, the RS_DRAMC_COECCE Register will hold the DRAM address that was being accessed when the ECC Error occurred. CECCRSI and RS_DRAMC_COECCE remain valid when interrupts are disabled and may be polled to detect error events. TUNPVI: The transmit unprovisioned error interrupt status bit reports an attempted data transmission to an unprovisioned channel FIFO. TUNPVI is set high upon attempts to write data to an unprovisioned channel FIFO. TUNPVI remains valid when interrupts are disabled and may be polled to detect an attempt to write data to an unprovisioned channel FIFO. UNTSXI: The Unexpected TSX interrupt status bit reports observation of invalid arrival of TSX to the microprocessor. UNTSXI is set high when such an event is reported. UNTSXI remains valid when interrupts are disabled and may be polled.
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Register 0x048 : F336 SBI DROP BUS Master Configuration Bit Bit 31 To Bit 2 Bit 1 To Bit 0 This register contains reserved bits. Reserved: The Reserved bits must be set to 0 for correct operation of the FREEDM336A1024 device. R/W Type Function Unused Default X
Reserved
0
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Register 0x04C : F336 SBI ADD BUS Master Configuration Bit Bit 31 To Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W DEFAULT_DRV Reserved Reserved CLK_MSTR 0 0 0 0 Type Function Unused Default X
This register configures the operation of the SBI ADD BUS. CLK_MSTR: The CLK_MSTR bit is used to specify whether the Insert block functions as a clock master or a clock slave. When this bit is a `1' the Insert block is a clock master. When set high, this bit overrides the individual tributary settings for clock master. The default state of this bit is clock slave. Reserved: The reserved bits must be set to 0 for correct operation of the FREEDM336A1024 device. DEFAULT_DRV: The Default Bus Driver selector bit (DEFAULT_DRV) enables the FREEDM336A1024 to drive the SBI ADD BUS when no other device is doing so. When set to 1, the INSBI336 will drive the bus whenever the ADETECT[1:0] inputs are both 0. When set to 0, the INSBI336 will only drive the bus when it has data to send (and when ADETECT[1:0] are both 0). It is recommended that one device connected to an SBI Bus be nominated as a default driver and configured to drive the bus when no other device is doing so.
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Register 0x068: DLL Configuration Bit Bit 31 To Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Reserved Reserved Unused ERRORE VERN_EN LOCK 0 0 X X 0 0 Type Function Unused Default X
The DLL Configuration Register controls the basic operation of the DLL. LOCK: The LOCK register is used to force the DLL to ignore phase offsets indicated by the phase detector after phase lock has been achieved. When LOCK is set to logic zero, the DLL will track phase offsets measured by the phase detector between the DLLSYSCLK and the DLLREFCLK inputs. When LOCK is set to logic one, the DLL will not change the tap after the phase detector indicates a zero phase offset between the DLLSYSCLK and the DLLREFCLK inputs for the first time. VERN_EN: The vernier enable register (VERN_EN) forces the DLL to ignore the phase detector and use the tap number specified by the VERNIER[7:0] register bits. When VERN_EN is set to logic zero, the DLL operates normally adjusting the phase offset based on the phase detector. When VERN_EN is set to logic one, the delay line uses the tap specified by the VERNIER[7:0] register bits. ERRORE: The ERROR interrupt enable (ERRORE) bit enables the error indication interrupt. When ERRORE is set high, an interrupt is generated upon assertion event of the ERR output and ERROR register. When ERRORE is set low, changes in the ERROR and ERR status do not generate an interrupt.
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Reserved: The reserved bits must be set low for correct operation of the FREEDM336A1024 device.
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Register 0x06C: DLL Vernier Control Bit Bit 31 To Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W VERNIER[7] VERNIER[6] VERNIER[5] VERNIER[4] VERNIER[3] VERNIER[2] VERNIER[1] VERNIER[0] 0 0 0 0 0 0 0 0 Type Function Unused Default X
The Vernier Control Register provides the delay line tap control when using the vernier option. VERNIER[7:0]: The vernier tap register bits (VERNIER[7:0]) specifies the phase delay through the DLL when using the vernier feature. When VERN_EN is set high, the VERNIER[7:0] registers specify the delay tap used. When VERN_EN is set low, the VERNIER[7:0] register is ignored. A VERNIER[7:0] value of all zeros specifies the delay tap with the minimum delay through the delay line. A VERNIER[7:0] value of 255 specifies the delay tap with the maximum delay through the delay line.
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Register 0x070: DLL Delay Tap Status Bit Bit 31 To Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W TAP[7] TAP[6] TAP[5] TAP[4] TAP[3] TAP[2] TAP[1] TAP[0] X X X X X X X X Type Function Unused Default X
The DLL Delay Tap Status Register indicates the delay tap used by the DLL to generate the outgoing clock. Writing to this register performs a software reset of the DLL. A software reset requires a maximum of 24*256 DLLSYSCLK cycles for the DLL to regain lock. During this time the DLLDCLKO phase is adjusting from its current position to delay tap 0 and back to a lock position. TAP[7:0]: The tap status register bits (TAP[7:0]) specifies the delay line tap the DLL is using to generate the outgoing clock DLLDCLKO. When TAP[7:0] is logic zero, the DLL is using the delay line tap with minimum phase delay. When TAP[7:0] is equal to 255, the DLL is using the delay line tap with maximum phase delay. TAP[7:0] is invalid when vernier enable VERN_EN is set to one.
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Register 0x074: DLL Control Status Bit Bit 31 To Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R DLLSYSCLKI DLLREFCLKI ERRORI CHANGEI Unused ERROR CHANGE RUN X X X X X X X X Type Function Unused Default X
The DLL Control Status Register provides information of the DLL operation. RUN: The DLL lock status register bit (RUN) indicates the DLL found a delay line tap in which the phase difference between the rising edge of DLLREFCLK and the rising edge of SYSLCK is zero. After system reset, RUN is logic zero until the phase detector indicates an initial lock condition. When the phase detector indicates lock, RUN is set to logic 1. The RUN register bit is cleared only by a hardware or a software reset. RUN is forced high when the VERN_EN register is set high. CHANGE: The delay line tap change register bit (CHANGE) indicates the DLL has moved to a new delay line tap. CHANGE is set high for eight DLLSYSCLK cycles when the DLL moves to a new delay line tap. ERROR: The delay line error register bit (ERROR) indicates the DLL has run out of dynamic range. When the DLL attempts to move beyond the end of the delay line, ERROR is set high. When ERROR is high, the DLL cannot generate a DLLDCLKO phase, which causes the rising edge of DLLREFCLK
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to be aligned to the rising edge of DLLSYSCLK. ERROR is set low, when the DLL captures lock again. ERROR is forced low when the VERN_EN register is set high. CHANGEI: The delay line tap change event register bit (CHANGEI) indicates the CHANGE register bit has changed value. When the CHANGE register changes from a logic zero to a logic one, the CHANGEI register bit is set to logic one. ERRORI: The delay line error event register bit (ERRORI) indicates the ERROR register bit has gone high. When the ERROR register changes from a logic zero to a logic one, the ERRORI register bit is set to logic one. If the ERRORE interrupt enable is high, the DLLI bit in the F336 Master High Priority Interrupt Status Register is also asserted when ERRORI asserts. DLLREFCLKI: The reference clock event register bit DLLREFCLKI provides a method to monitor activity on the reference clock. When the DLLREFCLK primary input changes from a logic zero to a logic one, the DLLREFCLKI register bit is set to logic one. DLLSYSCLKI: The system clock event register bit SYSLCKI provides a method to monitor activity on the system clock. When the DLLSYSCLK primary input changes from a logic zero to a logic one, the DLLSYSCLKI register bit is set to logic one. The DLLSYSCLKI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
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Register 0x100: RCAS Indirect Context RAM Link Select Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BUSY RWB SBI[2] SBI[1] SBI[0] SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0] 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register provides the link number used to access the RCAS context RAM. Writing to this register triggers an indirect register access. TRIB[4:0], SPE[1:0] and SBI[2:0]: The TRIB[4:0], SPE[1:0] and SBI[2:0] fields are used to fully specify to which SBI tributary the RCAS context RAM write or read operation will apply. TRIB[4:0] specifies the SBI tributary number within the SBI SPE as specified by the SPE[1:0] and SBI[2:0] fields. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Legal values for SBI[2:0] are b'001' through b`100'. RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the RCAS context RAM. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the LEN and SBI_MODE[2:0] bits of the RCAS Indirect context RAM Data register. Writing a logic one to RWB triggers an indirect read operation. The
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data read can be found in the LEN and SBI_MODE[2:0] bits of the RCAS Indirect context RAM Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written, to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the Indirect Data register or to determine when a new indirect write operation may commence.
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Register 0x104: RCAS Indirect Context RAM Data Bit Bit 31 To Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W SBI_MODE[2] SBI_MODE[1] SBI_MODE[0] LEN 0 0 0 0 Type Function Unused Default X
This register provides the link enable bit and the frame mode or data type associated to this particular link in the RCAS context RAM. SBI_MODE[2:0]: The SBI Frame Mode bits (SBI_MODE [2:0]), define the type of data for a specific link to be configured according to the following table. Table 17 - SBI Mode Configuration Single unframed unchannelized DS-3/Serial link 28 Unframed T1/J1 links 21 Unframed E1 links Unused Single framed unchannelized DS-3 28 Framed Channelized T1/J1 links 21 Framed Channelized E1 links Unused
SBI_MODE [2:0] 000 001 010 011 100 101 110 111
LEN: The Link Enable bit (LEN) when set Low disables the link. If enabled, the corresponding serial link must be disabled by clearing the appropriate SLINK[n] bit in register 0x114.
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Register 0x108: RCAS Indirect Channel Provision RAM Link Select Bit Bit 15 To Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SBI_MODE[2] SBI_MODE[1] SBI_MODE[0] SBI[2] SBI[1] SBI[0] SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register provides the link number used to access the RCAS channel provision RAM. SBI_MODE[2:0]: This field must be set to the same value as Bits3:1 in Register 0x104. TRIB[4:0], SPE[1:0] and SBI[2:0]: The TRIB[4:0], SPE[1:0] and SBI[2:0] fields are used to fully specify to which SBI tributary the context RAM write or read operation will apply. TRIB[4:0] specifies the SBI tributary number within the SBI SPE as specified by the SPE[1:0] and SBI[2:0] fields. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Legal values for SBI[2:0] are b'001' through b`100'.
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Register 0x10C: RCAS Indirect Channel Provision RAM Timeslot and control Select Bit Bit 31 To Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R/W R/W R/W R/W R/W R/W BUSY RWB TSLOT[4] TSLOT[3] TSLOT[2] TSLOT[1] TSLOT[0] 0 0 0 0 0 0 0 Type Function Unused Default X
This register provides the link timeslot number and control bits used to access the channel provision RAM. The RCAS Indirect Channel Provision RAM Link Select register must be valid before writing this register. Writing to this register triggers an indirect register access.
TSLOT[4:0]: The indirect timeslot number bits (TSLOT[4:0]) indicate the timeslot to be configured or interrogated in the indirect access. For a channelized T1/J1 link, timeslots 0 to 23 are valid. For a channelized E1 link, timeslots 0 to 31 are valid. For unchannelized links, only timeslot 0 is valid.
RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the RCAS channel provision RAM. The address to the channel provision RAM is constructed by combining the TSLOT[4:0] and LINK number. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the PROV, and the CHAN[9:0] bits of the Indirect Channel Data and Loopback enable register. Writing a logic one to RWB triggers an indirect read operation. Addressing of the RAM is the
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same as in an indirect write operation. The data read can be found in the PROV, and the CHAN[9:0] bits of the RCAS Indirect Channel Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written, to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the RCAS Indirect Data register or to determine when a new indirect write operation may commence.
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Register 0x110: RCAS Indirect Channel Data and Loopback enable Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CDLBEN PROV CHAN [9] CHAN [8] CHAN [7] CHAN [6] CHAN [5] CHAN [4] CHAN [3] CHAN [2] CHAN [1] CHAN [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register contains the data read from the RCAS channel provision RAM after an indirect read operation or the data to be inserted into the RCAS channel provision RAM in an indirect write operation. One channel must be reserved for timeslots that are unprovisioned in an active tributary. CHAN[9:0]: The indirect data bits (CHAN[9:0]) report the channel number read from the channel provision RAM after an indirect read operation has completed. Channel number to be written to the RCAS channel provision RAM in an indirect write operation must be set up in this register before triggering the write. CHAN[9:0] reflects the value written until the completion of a subsequent indirect read operation.
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PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the RCAS channel provision RAM after an indirect read operation has completed. The provision enable flag to be written to the RCAS channel provision RAM in an indirect write operation must be set up in this register before triggering the write. When PROV is set high, the current receive data byte is processed as part of the channel as indicated by CHAN[9:0]. When PROV is set low, the current timeslot does not belong to any channel and the received data byte ignored. PROV reflects the value written until the completion of a subsequent indirect read operation. CDLBEN: The indirect channel based diagnostic loopback enable bit (CDLBEN) indicates that for this channel, data is looped back from the Tx path (THDL12) instead of being received from the receive links. If enabled, the channel can not be used for serial or SBI traffic. In addition, the equivalent bandwidth must be disabled in normal mode operation.
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Register 0x114: RCAS Serial Link and Enable signal Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SLINK[11] SLINK[10] SLINK[9] SLINK [8] SLINK [7] SLINK [6] SLINK [5] SLINK [4] SLINK [3] SLINK [2] SLINK [1] SLINK [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register allows the selection of the receive serial link to be enabled. SLINK[11:0]: The receive Serial Link selection (SLINK[11:0]) specify the serial link to be activated, and its data and clock to be received from the RCAS-12. When SLINK[0] for example is set high, the data and clock on the particular selected serial link will be received, otherwise the serial link is ignored. When a serial link is enabled, the corresponding SBI/SPE on the SBI bus must be disabled. Serial links map to SBI links according to the following table:
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Table 18
- Serial Link to SBI Link Mapping Serial Link 0 1 2 3 4 5 6 7 8 9 10 11 SBI-SPE 1-1 2-1 3-1 4-1 1-2 2-2 3-2 4-2 1-3 2-3 3-3 4-3
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Register 0x200 : RHDL Indirect Channel Select Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 To Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Type Function Unused Default X
CBUSY CRWB Unused
0 0 X
CHAN[9] CHAN[8] CHAN[7] CHAN[6] CHAN[5] CHAN[4] CHAN[3] CHAN[2] CHAN[1] CHAN[0]
0 0 0 0 0 0 0 0 0 0
This register provides the channel number used to access the receive channel provision RAM. Writing to this register triggers an indirect channel register access. CHAN[9:0]: The indirect channel number bits (CHAN[9:0]) indicate the receive channel to be configured or interrogated in the indirect access. CRWB: The channel indirect access control bit (CRWB) selects between a configure (write) or interrogate (read) access to the receive channel provision RAM. Writing a logic zero to CRWB triggers an indirect write operation. Data to be written is taken from the Indirect Channel Data registers. Writing a logic one
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to CRWB triggers an indirect read operation. The data read can be found in the Indirect Channel Data registers. CBUSY: The indirect access status bit (CBUSY) reports the progress of an indirect access. CBUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, CBUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the RHDL Indirect Channel Data #1 and #2 registers or to determine when a new indirect write operation may commence.
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Register 0x204 : RHDL Indirect Channel Data Register #1 Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W* R/W W* R W W W W W W W W W W W W Type Function Unused Default X
PROV STRIP DELIN TAVAIL FPTR[11] FPTR[10] FPTR[9] FPTR[8] FPTR[7] FPTR[6] FPTR[5] FPTR[4] FPTR[3] FPTR[2] FPTR[1] FPTR[0]
X X X X X X X X X X X X X X X X
This register contains data read from the channel provision RAM after an indirect read operation or data to be inserted into the channel provision RAM in an indirect write operation. * These registers are also readable if no traffic is enabled in the device. FPTR[11:0]: The indirect FIFO block pointer (FPTR[11:0]) identifies one of the blocks of the circular linked list in the partial packet buffer used in the logical FIFO of the current channel. The FIFO pointer to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before
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triggering the write. The FIFO pointer value can be any one of the blocks provisioned to form the circular buffer. TAVAIL: The indirect Transaction Available bit (TAVAIL) indicates whether the FIFO for the channel currently contains at least one transaction, defined as either a complete packet or a transaction sized number of blocks, available for transfer over the receive DMA interface. When TAVAIL is a logic 1, a transaction is available for transfer. When TAVAIL is a logic 0, a transaction is not available. TAVAIL is a read-only bit. DELIN: The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag sequence delineation and bit de-stuffing on the incoming data stream. The delineate enable bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DELIN is set high, flag sequence delineation and bit de-stuffing is performed on the incoming data stream. When DELIN is set low, the HDLC processor does not perform any processing (flag sequence delineation, bit de-stuffing nor CRC verification) on the incoming stream. DELIN reflects the value written until the completion of a subsequent indirect channel read operation. STRIP: The indirect frame check sequence discard bit (STRIP) configures the HDLC processor to remove the CRC from the incoming frame when writing the data to the channel FIFO. The FCS discard bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When STRIP is set high and CRC[1:0] is not equal to "00", the received CRC value is not written to the FIFO. When STRIP is set low, the received CRC value is written to the FIFO. The bytes in buffer field of the RPD correctly reflect the presence/absence of CRC bytes in the buffer. The value of STRIP is ignored when DELIN is low. STRIP reflects the value written until the completion of a subsequent indirect channel read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect channel read operation has completed. The provision enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the HDLC processor will process data on the channel specified by CHAN[9:0]. When
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PROV is set low, the HDLC processor will ignore data on the channel specified by CHAN[9:0]. PROV reflects the value written until the completion of a subsequent indirect channel read operation.
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Register 0x208 : RHDL Indirect Channel Data Register #2 Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W W* W* R/W R/W W* W* W* Type Function Unused Default X
7BIT PRIORITY INVERT Unused CRC[1] CRC[0] Reserved Reserved Unused Unused Unused Unused Reserved Reserved Reserved Reserved
X X X X X X X X X X X X 0 0 0 0
This register contains data read from the channel provision RAM after an indirect read operation or it contains data to be inserted into the channel provision RAM in an indirect write operation. * These register bits are also readable if no traffic is enabled in the device. Reserved: The reserved bits must be set to the following values for correct operation of the FREEDM-336A1024 device.
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Table 19
- Reserved bit Settings Bit 9 8 3 2 1 0 Setting 0 0 0 0 0 1
CRC[1:0]: The CRC algorithm bits (CRC[1:0]) configures the HDLC processor to perform CRC verification on the incoming data stream. The value of CRC[1:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. CRC[1:0] is ignored when DELIN is low. CRC[1:0] reflects the value written until the completion of a subsequent indirect channel read operation. Table 20 - CRC[1:0] Settings CRC[1] 0 0 1 1 INVERT: The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert the incoming HDLC stream from the RCAS-12 before processing it. The value of INVERT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When INVERT is set to one, the HDLC stream is logically inverted before processing. When INVERT is set to zero, the HDLC stream is not inverted before processing. INVERT reflects the value written until the completion of a subsequent indirect channel read operation. Before tearing down a channel, this bit must be set to 0. PRIORITY: The channel FIFO priority bit (PRIORITY) informs the partial packet processor that the channel has precedence over other channels when being serviced by upstream blocks. The value of PRIORITY to be written to the CRC[0] 0 1 0 1 Operation No Verification CRC-CCITT CRC-32 Reserved
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channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. Channel FIFOs with PRIORITY set to one are serviced before channel FIFOs with PRIORITY set to zero. Channels with an HDLC data rate to FIFO size ratio that is significantly higher than other channels should have PRIORITY set to one. PRIORITY reflects the value written until the completion of a subsequent indirect channel read operation. 7BIT: The 7BIT enable bit (7BIT) configures the HDLC processor to ignore the least significant bit of each octet in the incoming channel stream. The value of 7BIT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When 7BIT is set high, the least significant bit (last bit of each octet received), is ignored. When 7BIT is set low, the entire receive data stream is processed. 7BIT reflects the value written until the completion of a subsequent indirect channel read operation.
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Register 0x210 : RHDL Indirect Block Select Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BLOCK[11] BLOCK[10] BLOCK[9] BLOCK[8] BLOCK[7] BLOCK[6] BLOCK[5] BLOCK[4] BLOCK[3] BLOCK[2] BLOCK[1] BLOCK[0] 0 0 0 0 0 0 0 0 0 0 0 0 R R/W Type Function Unused Default X
BBUSY BRWB Unused
0 0 X
This register provides the block number used to access the block pointer RAM. Writing to this register triggers an indirect block register access. BLOCK[11:0]: The indirect block number (BLOCK[11:0]) indicates the block to be configured or interrogated in the indirect access. BRWB: The block indirect access control bit (BRWB) selects between a configure (write) or interrogate (read) access to the block pointer RAM. Writing a logic zero to BRWB triggers an indirect block write operation. Data to be written is
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taken from the Indirect Block Data register. Writing a logic one to BRWB triggers an indirect block read operation. The data read can be found in the Indirect Block Data register. BBUSY: The indirect access status bit (BBUSY) reports the progress of an indirect access. BBUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BBUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the RHDL Indirect Block Data register or to determine when a new indirect write operation may commence.
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Register 0x214 : RHDL Indirect Block Data Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
BPTR[11] BPTR[10] BPTR[9] BPTR[8] BPTR[7] BPTR[6] BPTR[5] BPTR[4] BPTR[3] BPTR[2] BPTR[1] BPTR[0]
X X X X X X X X X X X X
This register contains data read from the block pointer RAM after an indirect block read operation or data to be inserted into the block pointer RAM in an indirect block write operation. BPTR[11:0]: The indirect block pointer (BPTR[11:0]) configures the block pointer of the block specified by the Indirect Block Select register. The block pointer to be written to the block pointer RAM, in an indirect write operation, must be set up in this register before triggering the write. The block pointer value is the block number of the next block in the linked list. A circular list of blocks must be formed in order to use the block list as a receive channel FIFO buffer. BPTR[11:0] reflects the value written until the completion of a subsequent indirect block read operation. When provisioning a channel FIFO, all block pointers must be re-written to properly initialize the FIFO.
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Register 0x220 : RHDL Configuration Bit Bit 31 To Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W LENCHK TSTD Unused Unused Unused Unused Unused Unused Unused Unused 0 0 X X X X X X X X Type Function Unused Default X
This register configures all provisioned receive channels. TSTD: The telecom standard bit (TSTD) controls the bit ordering of the HDLC data transferred across the receive APPI. When TSTD is set low, the least significant bit of each byte on the receive APPI bus (AD[0] and AD[8]) is the first HDLC bit received and the most significant bit of each byte (AD[7] and AD[15]) is the last HDLC bit received (datacom standard). When TSTD is set high, AD[0] and AD[8] are the last HDLC bits received and AD[7] and AD[15] are the first HDLC bits received (telecom standard). LENCHK: The packet length error check bit (LENCHK) controls the checking of receive packets that are longer than the maximum programmed length. When LENCHK is set high, receive packets are aborted and the remainder of the frame discarded when the packet exceeds the maximum packet length given by MAX[15:0]. When LENCHK is set low, receive packets are not checked for maximum size and MAX[15:0] must be set to `hFFFF.
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Register 0x224 : RHDL Maximum Packet Length Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
MAX[15] MAX[14] MAX[13] MAX[12] MAX[11] MAX[10] MAX[9] MAX[8] MAX[7] MAX[6] MAX[5] MAX[4] MAX[3] MAX[2] MAX[1] MAX[0]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
This register configures the maximum legal HDLC packet byte length. MAX[15:0]: The maximum HDLC packet length (MAX[15:0]) configures the FREEDM336A1024 to reject HDLC packets longer than a maximum size when LENCHK is set high. Receive packets with total length, including address, control, information and FCS fields, greater than MAX[15:0] bytes are aborted. When LENCHK is set low aborts are not generated regardless of packet length and MAX[15:0] must be set to `hFFFF.
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Register 0x380 : THDL Indirect Channel Select Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 To Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Type Function Unused Default X
CBUSY CRWB Unused
0 0 X
CHAN[9] CHAN[8] CHAN[7] CHAN[6] CHAN[5] CHAN[4] CHAN[3] CHAN[2] CHAN[1] CHAN[0]
0 0 0 0 0 0 0 0 0 0
This register provides the channel number used to access the transmit channel provision RAM. Writing to this register triggers an indirect channel register access. CHAN[9:0]: The indirect channel number bits (CHAN[9:0]) indicate the channel to be configured or interrogated in the indirect access. CRWB: The channel indirect access control bit (CRWB) selects between a configure (write) or interrogate (read) access to the channel provision RAM. Writing a logic zero to CRWB triggers an indirect write operation. Data to be written is taken from the Indirect Channel Data registers. Writing a logic one to CRWB
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triggers an indirect read operation. The data read can be found in the Indirect Channel Data registers. CBUSY: The indirect access status bit (CBUSY) reports the progress of an indirect access. CBUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, CBUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the THDL Indirect Channel Data #1, #2 and #3 registers or to determine when a new indirect write operation may commence.
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Register 0x384 : THDL Indirect Channel Data #1 Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
PROV CRC[1] CRC[0] DELIN FPTR[11] FPTR[10] FPTR[9] FPTR[8] FPTR[7] FPTR[6] FPTR[5] FPTR[4] FPTR[3] FPTR[2] FPTR[1] FPTR[0]
X X X X X X X X X X X X X X X X
This register contains data read from the channel provision RAM after an indirect channel read operation or data to be inserted into the channel provision RAM in an indirect channel write operation. FPTR[11:0]: The indirect FIFO block pointer (FPTR[11:0]) informs the partial packet buffer processor about the circular linked list of blocks to use for a FIFO for the channel. The FIFO pointer to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. The FIFO pointer value can be any one of the block numbers provisioned, by indirect block write operations, to form the circular buffer.
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DELIN: The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag sequence insertion and bit stuffing on the outgoing data stream. The delineate enable bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DELIN is set high, flag sequence insertion, bit stuffing and ,optionally, CRC generation is performed on the outgoing HDLC data stream. When DELIN is set low, the HDLC processor does not perform any processing (flag sequence insertion, bit stuffing nor CRC generation) on the outgoing stream. DELIN reflects the value written until the completion of a subsequent indirect channel read operation. CRC[1:0]: The CRC algorithm (CRC[1:0]) configures the HDLC processor to perform CRC generation on the outgoing HDLC data stream. The value of CRC[1:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. CRC[1:0] is ignored when DELIN is low. CRC[1:0] reflects the value written until the completion of a subsequent indirect channel read operation. Table 21 - CRC[1:0] Settings CRC[1] 0 0 1 1 PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect channel read operation has completed. The provision enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the HDLC processor will service requests for data from the TCAS-12 block. When PROV is set low, the HDLC processor will ignore requests from the TCAS-12 block. PROV reflects the value written until the completion of a subsequent indirect channel read operation. CRC[0] 0 1 0 1 Operation No CRC CRC-CCITT CRC-32 Reserved
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Register 0x388 : THDL Indirect Channel Data #2 Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
7BIT INHIBIT INVERT DFCS Reserved FLEN[10] FLEN[9] FLEN[8] FLEN[7] FLEN[6] FLEN[5] FLEN[4] FLEN[3] FLEN[2] FLEN[1] FLEN[0]
X X X X 0 X X X X X X X X X X X
This register contains data to be inserted into the channel provision RAM in an indirect write operation. FLEN[10:0]: The indirect FIFO length (FLEN[10:0]) is the number of blocks, less one, that is provisioned to the circular channel FIFO specified by the FPTR[10:0] block pointer. The FIFO length to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write.
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
Reserved: The reserved bits must be set low for correct operation of the FREEDM336A1024 device. DFCS: The diagnose frame check sequence bit (DFCS) controls the inversion of the FCS field inserted into the transmit packet. The value of DFCS to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DFCS is set to one, the FCS field in the outgoing HDLC stream is logically inverted allowing diagnosis of downstream FCS verification logic. The outgoing FCS field is not inverted when DFCS is set to zero. DFCS reflects the value written until the completion of a subsequent indirect channel read operation. INVERT: The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert the outgoing HDLC stream. The value of INVERT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When INVERT is set to one, the outgoing HDLC stream is logically inverted. The outgoing HDLC stream is not inverted when INVERT is set to zero. INVERT reflects the value written until the completion of a subsequent indirect channel read operation. INHIBIT: The channel FIFO expedite inhibit bit (INHIBIT) informs the partial packet processor that the channel has less priority than other channels when requesting data from the EQM-12. The value of INHIBIT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. Channel FIFOs with INHIBIT set to one cannot make expedited requests for data to the EQM-12. When INHIBIT is set to zero, both normal and expedited requests can be made to the EQM12. Channels with HDLC data rates significantly slower than other channels should have INHIBIT set to one. INHIBIT reflects the value written until the completion of a subsequent indirect channel read operation. 7BIT: The least significant stuff enable bit (7BIT) configures the HDLC processor to stuff the least significant bit of each octet in the outgoing channel stream. The value of 7BIT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When 7BIT is set high, the least significant bit (last bit of each octet transmitted) does not contain channel data and is forced to the value configured by the BIT8 register bit. When 7BIT is set low, the entire octet
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contains valid data and BIT8 is ignored. 7BIT reflects the value written until the completion of a subsequent indirect channel read operation.
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Register 0x38C : THDL Indirect Channel Data #3 Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
TRANS IDLE Unused Unused LEVEL[3] LEVEL[2] LEVEL[1] LEVEL[0] FLAG[2] FLAG[1] FLAG[0] Unused XFER[3] XFER[2] XFER[1] XFER[0]
X X X X X X X X X X X X X X X X
This register contains data read from the channel provision RAM after an indirect read operation or data to be inserted into the channel provision RAM in an indirect. XFER[3:0]: The indirect channel transfer size (XFER[3:0]) specifies the minimum FIFO free space, less 1, before the partial packet processor begins requesting data from the DMA port. The channel transfer size to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When the channel FIFO free space reaches the limit specified by XFER[3:0], the partial packet processor will make a request to the DMA port for one XFER[3:0] amount of data. FIFO free space is
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measured in the number of blocks with each block being 16 bytes in size. XFER[3:0] reflects the value written until the completion of a subsequent indirect channel read operation. XFER[3:0] must be less than or equal to the start transmission level specified by LEVEL[3:0] and TRANS. FLAG[2:0]: The flag insertion control (FLAG[2:0]) configures the minimum number of flags or bytes of idle bits the HDLC processor inserts between HDLC packets. The value of FLAG[2:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. The minimum number of flags or bytes of idle (8 bits of 1's) inserted between HDLC packets is shown in the table below. FLAG[2:0] reflects the value written until the completion of a subsequent indirect channel read operation. Table 22 - FLAG[2:0] Settings FLAG[2:0] 000 001 010 011 100 101 110 111 LEVEL[3:0]: The indirect channel FIFO trigger level (LEVEL[3:0]), in concert with the TRANS bit, configure the various channel FIFO free space levels which trigger the HDLC processor to start transmission of a HDLC packet as well as trigger the partial packet buffer to request data from the upstream device as shown in the following table. The channel FIFO trigger level to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. LEVEL[3:0] reflects the value written until the completion of a subsequent indirect channel read operation. Minimum Number of Flag/Idle Bytes 1 flag / 0 Idle byte 2 flags / 0 idle byte 4 flags / 2 idle bytes 8 flags / 6 idle bytes 16 flags / 14 idle bytes 32 flags / 30 idle bytes 64 flags / 62 idle bytes 128 flags / 126 idle bytes
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The HDLC processor starts transmitting a packet when the channel FIFO free space is less than or equal to the level specified in the appropriate Start Transmission Level column of the following table or when an end of a packet is stored in the channel FIFO. When the channel FIFO free space is greater than or equal to the level specified in the Starving Trigger Level column of the following table and the HDLC processor is transmitting a packet and an end of a packet is not stored in the channel FIFO, the partial packet buffer makes expedited requests to the upstream device to retrieve 32 bytes of data. IDLE: The interframe time fill bit (IDLE) configures the HDLC processor to use flag bytes or HDLC idle as the interframe time fill between HDLC packets. The value of IDLE to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When IDLE is set low, the HDLC processor uses flag bytes as the interframe time fill. When IDLE is set high, the HDLC processor uses HDLC idle (all one's bit with no bit-stuffing pattern is transmitted) as the interframe time fill. IDLE reflects the value written until the completion of a subsequent indirect channel read operation. TRANS: The indirect transmission start bit (TRANS), in concert with the LEVEL[3:0] bits, configure the various channel FIFO free space levels which trigger the HDLC processor to start transmission of a HDLC packet as well as trigger the partial packet buffer to request data from the upstream device as shown in the following table. The transmission start mode to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. TRANS reflects the value written until the completion of a subsequent indirect channel read operation. The HDLC processor starts transmitting a packet when the channel FIFO free space is less than or equal to the level specified in the appropriate Start Transmission Level column of the following table or when an end of a packet is stored in the channel FIFO. When the channel FIFO free space is greater than or equal to the level specified in the Starving Trigger Level column of the following table and the HDLC processor is transmitting a packet and an end of a packet is not stored in the channel FIFO, the partial packet buffer makes expedited requests to the upstream device to retrieve 32 bytes of data. To prevent lockup, the start transmission level must be set to 48 bytes or greater or to a value such that the FIFO size less the start transmission level is a multiple of 32 bytes.
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Table 23
- Level[3:0]/TRANS Settings Starving Trigger Level 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 64 Blocks (1 Kbytes free) 96 Blocks (1.5 Kbytes free) 192 Blocks (3 Kbytes free) Start Transmission Level (TRANS=0) Invalid 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 64 Blocks (1 Kbytes free) 128 Blocks (2 Kbytes free) Start Transmission Level (TRANS=1) 2 Blocks (32 bytes free) Invalid 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 96 Blocks (1.5 Kbytes free)
LEVEL[3:0]
0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
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Register 0x390 : THDL Indirect Channel Data Register #4 Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R R R R R Type Function Unused Default X
DMAEXP DMAREQ AVAIL EOP[12] EOP[11] EOP[10] EOP[9] EOP[8] EOP[7] EOP[6] EOP[5] EOP[4] EOP[3] EOP[2] EOP[1] EOP[0]
X X X X X X X X X X X X X X X X
This register contains data read from the channel provision RAM after an indirect read operation. EOP[12:0]: The indirect channel FIFO end of packet count (EOP[12:0]) specifies the number of end of packets stored in the channel FIFO. The value of EOP[12:0] is expressed in a signed 2's complement form with EOP[12] as the sign bit. EOP[12:0] reflects the value of the last indirect channel read operation. The EOP[12:0] register bits are used for test purposes only.
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AVAIL: The indirect channel data available flag (AVAIL) indicates when sufficient packet data is store in the channel FIFO for the HDLC processor to start transmission. When AVAIL is high, the channel FIFO free space is less than or equal to the level specified by the TRANS and LEVEL[3:0] register bits or at least one end of packet is store in the channel FIFO. In this case, the HDLC processor starts transmission when AVAIL is high and sufficient flags/idle specified by FLAG[2:0] have been transmitted. When AVAIL is low, the channel FIFO free space is greater than the level specified by the TRANS and LEVEL[3:0] register bits and no end of packets are store in the channel FIFO. In this case, the HDLC processor will not start transmitting a new packet or will finish transmitting the current packet. AVAIL reflects the value of the last indirect channel read operation. The AVAIL register bit is used for test purposes only. DMAREQ: The indirect channel service request flag (DMAREQ) indicates when sufficient free space exists in the channel FIFO to perform a DMA operation. When DMAREQ is high, the channel free space is greater than or equal to 32 bytes. When DMAREQ is low, the channel free space is less than 32 bytes. DMAREQ reflects the value of the last indirect channel read operation. The DMAREQ register bit is used for test purposes only. DMAEXP: The indirect channel expedite service request flag (DMAEXP) indicates when the channel FIFO requires an expedited DMA operation. When DMAEXP is high, the channel free space is greater than or equal to the level specified by LEVEL[3:0] and the HDLC processor is transmitting a packet and the end of a packet is not store in the channel FIFO. When DMAEXP is low, the channel free space is less than the level specified by LEVEL[3:0], or the HDLC processor is not transmitting or an end of a packet is store in the channel FIFO. DMAEXP reflects the value of the last indirect channel read operation. The DMAEXP register bit is used for test purposes only.
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Register 0x394 : THDL Indirect Channel Data Register #5 Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R R Type Function Unused Default X
Unused Unused Unused FREE[12] FREE[11] FREE[10] FREE[9] FREE[8] FREE[7] FREE[6] FREE[5] FREE[4] FREE[3] FREE[2] FREE[1] FREE[0]
X X X X X X X X X X X X X X X X
This register contains data read from the channel provision RAM after an indirect read operation. FREE[12:0]: The indirect channel FIFO free space (FREE[12:0]) indicates the number of empty or free blocks in the channel FIFO. The value of FREE[12:0] is expressed in a signed 2's complement form with FREE[12] as the sign bit. FREE[12:0] reflects the value of the last indirect channel read operation. The FREE[12:0] register bits are used for test purposes only.
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Register 0x398 : THDL Indirect Channel Data Register #6 Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R Type Function Unused Default X
Unused Unused Unused Unused WPTR[11] WPTR[10] WPTR[9] WPTR[8] WPTR[7] WPTR[6] WPTR[5] WPTR[4] WPTR[3] WPTR[2] WPTR[1] WPTR[0]
X X X X X X X X X X X X X X X X
This register contains data read from the channel provision RAM after an indirect read operation. WPTR[11:0]: The channel FIFO writer pointer (WPTR[11:0]) is the block number in the channel FIFO to which the write processor is storing packet data. WPTR[11:0] reflects the value of the last indirect channel read operation. The WPTR[11:0] register bits are used for test purposes only.
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Register 0x3A0 : THDL Indirect Block Select Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BLOCK[11] BLOCK[10] BLOCK[9] BLOCK[8] BLOCK[7] BLOCK[6] BLOCK[5] BLOCK[4] BLOCK[3] BLOCK[2] BLOCK[1] BLOCK[0] 0 0 0 0 0 0 0 0 0 0 0 0 R R/W Type Function Unused Default X
BBUSY BRWB Unused
0 0 X
This register provides the block number used to access the block pointer RAM. Writing to this register triggers an indirect block register access. BLOCK[11:0]: The indirect block number (BLOCK[11:0]) indicates the block to be configured or interrogated in the indirect access. BRWB: The block indirect access control bit (BRWB) selects between a configure (write) or interrogate (read) access to the block pointer RAM. Writing a logic zero to BRWB triggers an indirect block write operation. Data to be written is
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taken from the Indirect Block Data register. Writing a logic one to BRWB triggers an indirect block read operation. The data read can be found in the Indirect Block Data register. BBUSY: The indirect access status bit (BBUSY) reports the progress of an indirect access. BBUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BBUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the THDL Indirect Block Data register or to determine when a new indirect write operation may commence.
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Register 0x3A4 : THDL Indirect Block Data Bit Bit 31 To Bit 16 Bit 15 Bit 14 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
Reserved Unused
0 X
BPTR[11] BPTR[10] BPTR[9] BPTR[8] BPTR[7] BPTR[6] BPTR[5] BPTR[4] BPTR[3] BPTR[2] BPTR[1] BPTR[0]
0 0 0 0 0 0 0 0 0 0 0 0
This register contains data read from the transmit block pointer RAM after an indirect block read operation or data to be inserted into the transmit block pointer RAM in an indirect block write operation. BPTR[11:0]: The indirect block pointer (BPTR[11:0]) configures the block pointer of the block specified by the Indirect Block Select register. The block pointer to be written to the transmit block pointer RAM, in an indirect write operation, must be set up in this register before triggering the write. The block pointer value is the block number of the next block in the linked list. A circular list of blocks must be formed in order to use the block list as a channel FIFO buffer. FPTR[11:0] reflects the value written until the completion of a subsequent indirect block read operation.
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When provisioning a channel FIFO, all blocks pointers must be re-written to properly initialize the FIFO.
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Register 0x3B0 : THDL Configuration Bit Bit 31 To Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 To Bit 4 Bit 3 To Bit 0 R/W R/W R/W R/W Type Function Unused Default X
BIT8 TSTD Reserved Unused
0 0 0 X
Reserved
0
This register configures all provisioned channels. Reserved: The reserved bits must be set low for correct operation of the FREEDM336A1024 device. TSTD: The telecom standard bit (TSTD) controls the bit ordering of the HDLC data transferred on the transmit APPI. When TSTD is set low, the least significant bit of the each byte on the transmit APPI bus (AD[0] and AD[8]) is the first HDLC bit transmitted and the most significant bit of each byte (AD[7] and AD[15]) is the last HDLC bit transmitted (datacom standard). When TSTD is set high, AD[0] and AD[8] are the last HDLC bit transmitted and AD[7] and AD[15] are the first HDLC bit transmitted (telecom standard). BIT8: The least significant stuff control bit (BIT8) carries the value placed in the least significant bit of each octet when the HDLC processor is configured (7BIT set high) to stuff the least significant bit of each octet in the corresponding transmit link (TD[n]). When BIT8 is set high, the least significant bit (last bit of each octet transmitted) is forced high. When BIT8 is set low, the least significant bit is forced low. BIT8 is ignored when 7BIT is set low.
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Register 0x400 : TCAS Indirect Context RAM Link Select Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
BUSY RWB SBI[2] SBI[1] SBI[0] SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0]
X 0 0 0 0 0 0 0 0 0 0 0
This register provides the link number used to access the TCAS Context RAM. Writing to this register triggers an indirect register access. TRIB[4:0], SPE[1:0] and SBI[2:0]: The TRIB[4:0], SPE[1:0] and SBI[2:0] fields are used to fully specify to which SBI tributary the context RAM write or read operation will apply. TRIB[4:0] specifies the SBI tributary number within the SBI SPE as specified by the SPE[1:0] and SBI[2:0] fields. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Legal values for SBI[2:0] are b'001' through b`100'. RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the context RAM. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the LEN and SBI_MODE[2:0] bits of the TCAS Indirect Context RAM Data register. Writing a logic one to RWB triggers an indirect read operation. The data read
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can be found in the LEN and SBI_MODE[2:0] bits of the TCAS Indirect context RAM Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written, to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the TCAS Indirect Data register or to determine when a new indirect write operation may commence.
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Register 0x404 : TCAS Indirect Context RAM Data Bit Bit 31 To Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type Function Unused Default X
SYNC SBI_MODE[2] SBI_MODE[1] SBI_MODE[0] LEN
0 0 0 0 0
This register provides the link enable bit and the frame mode or data type associated to this particular link in the TCAS context RAM. SYNC: The SYNC bit determines whether the link is operating in synchronous mode or asynchronous mode. When set low the link is set to asynchronous mode. When set high the TCAS will to synchronize the link output data according to the synchronous mode requirements of the SBI bus. This bit only applies to framed T1 or E1 links. SBI_MODE[2:0]: The Frame Mode bits (SBI_MODE [2:0]), report the type of data to a specific link to be configured accordingly according to the table below. Table 24 - SBI Mode Configuration Single unframed unchannelized DS-3/Serial Link 28 Unframed T1/J1 links 21 Unframed E1 links Unused Single framed unchannelized DS-3 28 Framed Channelized T1/J1 links 21 Framed Channelized E1 links unused
SBI_MODE [2:0] 000 001 010 011 100 101 110 111
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LEN: The Link Enable bit (LEN) when set Low disables the link. If enabled, the corresponding serial link must be disabled by clearing the appropriate SLINK[n] bit in register 0x414.
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Register 0x408 : TCAS Indirect Channel Provision RAM Select Bit Bit 31 To Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
SBI_MODE[2] SBI_MODE[1] SBI_MODE[0] SBI[2] SBI[1] SBI[0] SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0]
0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the link number used to access the TCAS channel provision RAM. SBI_MODE[2:0]: This field must be set to the same value as Bits3:1 in Register 0x404. TRIB[4:0], SPE[1:0] and SBI[2:0]: The TRIB[4:0], SPE[1:0] and SBI[2:0] fields are used to fully specify to which SBI tributary the context RAM write or read operation will apply. TRIB[4:0] specifies the SBI tributary number within the SBI SPE as specified by the SPE[1:0] and SBI[2:0] fields. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Legal values for SBI[2:0] are b'001' through b`100'.
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Register 0x40C : TCAS Indirect Channel Provision RAM Timeslot and Control Select Bit Bit 31 To Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R/W R/W R/W R/W R/W R/W Type Function Unused Default X
BUSY RWB TSLOT[4] TSLOT[3] TSLOT[2] TSLOT[1] TSLOT[0]
0 0 0 0 0 0 0
This register provides the link timeslot number and control bits used to access the TCAS channel provision RAM. Writing to this register triggers an indirect register access. TSLOT[4:0]: The indirect timeslot number bits (TSLOT[4:0]) indicate the timeslot to be configured or interrogated in the indirect access. For a channelized T1/J1 link, timeslots 0 to 23 are valid. For a channelized E1 link, timeslots 0 to 31 are valid. For unchannelized links, only timeslot 0 is valid. RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the TCAS channel provision RAM. The address to the TCAS channel provision RAM is constructed by combining the TSLOT[4:0] and LINK[9:0] bits. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the PROV, and the CHAN[9:0] bits of the TCAS Indirect Channel Data register. Writing a logic one to RWB triggers an indirect read operation. Addressing of the RAM is the same as in an indirect write operation. The data read can be found in the PROV, and the CHAN[9:0] bits of the TCAS Indirect Channel Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written, to trigger an indirect
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access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the Indirect Data register or to determine when a new indirect write operation may commence.
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Register 0x410: TCAS Indirect Channel Data enable Bit Bit 31 To Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PROV CHAN [9] CHAN [8] CHAN [7] CHAN [6] CHAN [5] CHAN [4] CHAN [3] CHAN [2] CHAN [1] CHAN [0] 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register contains the data read from the TCAS channel provision RAM after an indirect read operation or the data to be inserted into the TCAS channel provision RAM in an indirect write operation. CHAN[9:0]: The indirect data bits (CHAN[9:0]) report the channel number read from the channel provision RAM after an indirect read operation has completed. Channel number to be written to the channel provision RAM in an indirect write operation must be set up in this register before triggering the write. CHAN[9:0] reflects the value written until the completion of a subsequent indirect read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the TCAS channel provision RAM after an indirect read operation has completed. The provision enable flag to be written to the TCAS channel provision RAM in an indirect write operation must be set up in this register before triggering the write. When PROV is set high, the current
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request is processed as part of the channel as indicated by CHAN[9:0]. When PROV is set low, the current timeslot does not belong to any channel and the request is ignored. PROV reflects the value written until the completion of a subsequent indirect read operation. For unchannelized links, a read of any TSLOT will report the value in TSLOT[4:0]=00000.
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Register 0x414: TCAS Serial Link Enable Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SLINK[11] SLINK[10] SLINK[9] SLINK [8] SLINK [7] SLINK [6] SLINK [5] SLINK [4] SLINK [3] SLINK [2] SLINK [1] SLINK [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
This register allows the selection of the serial link to be activated. SLINK[11:0]: The Tx Serial Link selection (SLINK[11:0]) bits specify the serial links to be activated. When SLINK[x] is set high, the data on the particular selected serial link will be transmitted, otherwise the serial link is ignored. When a serial link is enabled, the corresponding SBI/SPE on the SBI bus must be disabled. Serial links map to SBI links according to the following table:
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Table 25
- Serial Link to SBI Link Mapping Serial Link 0 1 2 3 4 5 6 7 8 9 10 11 SBI-SPE 1-1 2-1 3-1 4-1 1-2 2-2 3-2 4-2 1-3 2-3 3-3 4-3
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Register 0x418 : TCAS Idle Time-slot Fill Data Bit Bit 31 To Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
FDATA[7] FDATA[6] FDATA[5] FDATA[4] FDATA[3] FDATA[2] FDATA[1] FDATA[0]
1 1 1 1 1 1 1 1
This register contains the data to be written to disabled time-slots of a channelized link. FDATA[7:0]: The fill data bits (FDATA[7:0]) are transmitted during disabled (PROV set low) time-slots of channelized links.
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Register 0x580: RAPI Control Register Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 To Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 To Bit 0 R/W R/W R/W R/W R/W Type Function Unused Default X
ENABLE STATEN Reserved Unused
0 0 0 X
ANYPHYL Unused ALL1ENB Unused
0 X 1 X
The Control Register is used to set the operating mode of RAPI-12. It is used to configure the final word of a packet in APPI. It is also used to enable the RAPI12. ALL1ENB: The All Ones Enable bit (ALL1ENB) is used to configure the device address space of the RAPI-12 in level-2 APPI. It is not used in level-3 APPI. When ALL1ENB is high in level-2 APPI, the all ones address (RXADDR[3:0] = "1111") is reserved as null address to resolve contention for ANY-PHY bus, and it can not be assigned to any RAPI-12. When ALL1ENB is low in level-2 APPI, the all ones address is not treated as null address, and it can be assigned to one RAPI-12; contention for ANY-PHY bus must be resolved by external logic. ANYPHYL: The ANY PHY Level select bit allows selection between ANY PHY Level 2 and ANY PHY Level 3.
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Table 26
- ANY-PHY Encoding ANY-PHY 0 1 ANY-PHY Level Level 2 Level 3
Reserved: The reserved bit must be set low for correct operation of the FREEDM336A1024 device. STATEN: The status enable bit (STATEN) enables the RAPI-12 to provide the status of an erred packet on RXDATA[7:0] during transfer of the final word of that packet on the receive APPI (REOP and RERR high). When STATEN is set high, the RAPI-12 overwrites RXDATA[7:0] of the final word of an erred packet with status information for that packet. When STATEN is set low, the RAPI-12 does not report detailed status information for an erred packet. The RXDATA[15:0] connector description details the erred packet status reporting when STATEN is set high. ENABLE: The Enable bit (ENABLE) enables normal operation of the RAPI-12. When ENABLE is set low, the RAPI-12 will complete the current data transfer and will respond to any further transactions on the APPI but not send any new data. When ENABLE is set high, the RAPI-12 operates normally.
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Register 0x584: RAPI Device Base Address Register Bit Bit 31 To Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W DBADDR[3] DBADDR[2] DBADDR[1] DBADDR[0] 0 0 0 0 Type Function Unused Default X
The Device Base Address Register is used to configure the address space occupied by the FREEDM-336A1024 device for device selection. DBADDR[3:0]: The Device Base Address bits (DBADDR[3:0]) configure the address space occupied by the FREEDM-336A1024 device for purposes of responding to receive polling and receive device selection. During polling in Level-2 APPI, the DBADDR[3:0] bits are used to respond to polling via the RXADDR[3:0] pins. Polling is not used in Level-3 APPI. During device selection, the DBADDR[3:0] bits are used to select a FREEDM-336A1024 device, enabling it to output data on the receive APPI.
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Register 0x588: RAPI Channel Base Address Register Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CBADDR[15] CBADDR[14] CBADDR[13] CBADDR[12] CBADDR[11] CBADDR[10] CBADDR[9] CBADDR[8] CBADDR[7] CBADDR[6] CBADDR[5] CBADDR[4] CBADDR[3] CBADDR[2] CBADDR[1] CBADDR[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
The Channel Base Address Register is used to configure the address space occupied by the FREEDM-336A1024 device for receive polling. CBADDR[15:0]: The Channel Base Address bits (CBADDR[15:0]) configure the FREEDM336A1024 to support channel numbers starting from the channel Base Address. The channel numbers used by the FREEDM-336A1024 will be CBADDR[15:0] to CBADDR[15:0]+1023.
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Register 0x58C: RAPI Status Register Bit Bit 31 To Bit 2 Bit 1 Bit 0 R R Type Function Unused Default X
UDRUN Reserved
1 0
The Status Register is used to record the status of RAPI-12. UDRUN: The underrun bit (UDRUN) is used to record events when the circular FIFO in RAPI-12 is empty. Reserved :
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Register 0x5C0 : SBI EXTRACT Control Bit Bit 31 To Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type Function Unused Default X
Reserved FIFO_UDRE Unused TS_EN Reserved SBI_PAR_CTL
0 X 0 1
This register controls the operation of the SBI EXTRACT block. SBI_PAR_CTL The SBI_PAR_CTL bit is used to configure the Parity mode for checking of the SBI parity signal, DDP as follows: When SBI_PAR_CTL is '0' parity is even. When SBI_PAR_CTL is `1' parity is odd. Reserved: The reserved bits must be set according to the table below for correct operation of the FREEDM-336A1024 device. Table 27 - Reserved/Unused bit Settings Bit 3 2 1 Setting 1 0 0
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Register 0x5D4 : SBI EXTRACT Tributary Indirect Access Address Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
BUSY RWB Reserved Reserved Unused Reserved SBI[2] SBI[1] SBI[0] SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0]
0 0 0 0 X 0 0 0 0 0 0 0 0 0 0 0
This register provides the receive SBI, SPE and link number used to access the SBI EXTRACT tributary control configuration RAM. TRIB[4:0], SPE[1:0] and SBI[2:0]: The TRIB[4:0], SPE[1:0] and SBI[2:0] fields are used to fully specify to which SBI tributary the Control register write or read operation will apply. TRIB[4:0] specifies the SBI tributary number within the SBI SPE as specified by the SPE[1:0] and SBI[2:0] fields. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Legal values for SBI[2:0] are b'001' through b`100'.
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Reserved: The reserved bit must be set low for correct operation of the FREEDM336A1024 device. RWB The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the tributary control configuration RAM. Writing a `0' to RWB triggers an indirect write operation. Data to be written is taken from the SBI EXTRACT Tributary Indirect Access Data Register. Writing a `1' to RWB triggers an indirect read operation. The data read can be found in the SBI EXTRACT Tributary Indirect Access Data Register. BUSY The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when a write to the Extract RAM Indirect Access Address Register triggers an indirect access and will stay high until the access is complete. This bit should be polled to determine when data from an indirect read operation is available in the Extract RAM Indirect Access Control Data Register. In a write access this bit should be polled to determine when a new operation may commence.
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Register 0x5DC : SBI EXTRACT Tributary RAM Indirect Access Data Bit Bit 31 To Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
Reserved Reserved Reserved TRIB_TYP[1] TRIB_TYP[0] Reserved ENBL
0 0 0 0 0 0 0
This register contains data read from the SBI EXTRACT tributary control configuration RAM after an indirect read operation or data to be written to the tributary control configuration RAM in an indirect write operation. ENBL The ENBL bit is used to enable the EXSBI to take tributary data from an SBI tributary and transmit that data to the SBIIP link. Reserved: The reserved bits must be set low for correct operation of the FREEDM336A1024 device. TRIB_TYP[1:0] The TRIB_TYP[1:0] field is used to specify the characteristics of the SBI tributary as shown in Table 28 below: Table 28 - TRIB_TYP Encoding Tributary type Reserved Framed Unframed Reserved
TRIB_TYP[1:0] 00 01 10 11
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Register 0x5E0H: SBI EXTRACT SBI1 SPE Configuration Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SPE3_EN SPE3_TYP[2] SPE3_TYP [1] SPE3_TYP [0] SPE2_EN SPE2_TYP[2] SPE2_TYP [1] SPE2_TYP [0] SPE1_EN SPE1_TYP[2] SPE1_TYP [1] SPE1_TYP [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type R Function Unused Default 0
SPE1_EN, SPE2_EN, SPE3_EN: Enables SPE1, SPE2 and SPE3 respectively in SBI1. When these bits are set to 0 the respective SPE in SBI1 is disabled. When these bits are set to 1 the respective SPE in SBI1 is enabled. When an SPE is enabled each individual tributary within an SPE can be selectively enabled via the Extract Tributary RAM Indirect Access Control Data register. These bits must be written in a second write after the SPE*_TYP[2:0] bits have been set. SPE1_TYP[2:0], SPE2_TYP[2:0], SPE3_TYP[2:0]: SPE1_TYP[2:0], SPE2_TYP[2:0] and SPE3_TYP[2:0] select the SPE type for the three SPEs within SBI1 respectively. The types for each SPE are independently configured with possible types being T1, E1, DS3 or Fractional Rate. The settings for SPEx_TYP[2:0] are:
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Table 29
- SBI EXTRACT SPE_TYP[2:0] SPEx_TYP[2:0] X00 X01 010 011 11X Payload Type 28 T1/J1 links 21 E1links Single DS3 Link Unused Fractional Rate
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Register 0x5E4H: SBI EXTRACT SBI2 SPE Configuration Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SPE3_EN SPE3_TYP[2] SPE3_TYP [1] SPE3_TYP [0] SPE2_EN SPE2_TYP[2] SPE2_TYP [1] SPE2_TYP [0] SPE1_EN SPE1_TYP[2] SPE1_TYP [1] SPE1_TYP [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type R Function Unused Default 0
SPE1_EN, SPE2_EN, SPE3_EN: Enables SPE1, SPE2 and SPE3 respectively in SBI2. When these bits are set to 0 the respective SPE in SBI2 is disabled. When these bits are set to 1 the respective SPE in SBI2 is enabled. When an SPE is enabled each individual tributary within an SPE can be selectively enabled via the Extract Tributary RAM Indirect Access Control Data register. These bits must be written in a second write after the SPE*_TYP[2:0] bits have been set. SPE1_TYP[2:0], SPE2_TYP[2:0], SPE3_TYP[2:0]: SPE1_TYP[2:0], SPE2_TYP[2:0] and SPE3_TYP[2:0] select the SPE type for the three SPEs within SBI2 respectively. The types for each SPE are independently configured with possible types being T1, E1, DS3 or Fractional Rate. The settings for SPEx_TYP[2:0] are:
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Table 30
- SBI EXTRACT SPE_TYP[2:0] SPEx_TYP[2:0] X00 X01 010 011 11X Payload Type 28 T1/J1 links 21 E1links Single DS3 Link Unused Fractional Rate
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Register 0x5E8H: SBI EXTRACT SBI3 SPE Configuration Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SPE3_EN SPE3_TYP[2] SPE3_TYP [1] SPE3_TYP [0] SPE2_EN SPE2_TYP[2] SPE2_TYP [1] SPE2_TYP [0] SPE1_EN SPE1_TYP[2] SPE1_TYP [1] SPE1_TYP [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type R Function Unused Default 0
SPE1_EN, SPE2_EN, SPE3_EN: Enables SPE1, SPE2 and SPE3 respectively in SBI3. When these bits are set to 0 the respective SPE in SBI3 is disabled. When these bits are set to 1 the respective SPE in SBI3 is enabled. When an SPE is enabled each individual tributary within an SPE can be selectively enabled via the Extract Tributary RAM Indirect Access Control Data register. These bits must be written in a second write after the SPE*_TYP[2:0] bits have been set. SPE1_TYP[2:0], SPE2_TYP[2:0], SPE3_TYP[2:0]: SPE1_TYP[2:0], SPE2_TYP[2:0] and SPE3_TYP[2:0] select the SPE type for the three SPEs within SBI2 respectively. The types for each SPE are independently configured with possible types being T1, E1, DS3 or Fractional Rate. The settings for SPEx_TYP[2:0] are:
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Table 31
- SBI EXTRACT SPE_TYP[2:0] SPEx_TYP[2:0] X00 X01 010 011 11X Payload Type 28 T1/J1 links 21 E1links Single DS3 Link Unused Fractional Rate
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Register 0x5ECH: SBI EXTRACT SBI4 SPE Configuration Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SPE3_EN SPE3_TYP[2] SPE3_TYP [1] SPE3_TYP [0] SPE2_EN SPE2_TYP[2] SPE2_TYP [1] SPE2_TYP [0] SPE1_EN SPE1_TYP[2] SPE1_TYP [1] SPE1_TYP [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type R Function Unused Default 0
SPE1_EN, SPE2_EN, SPE3_EN: Enables SPE1, SPE2 and SPE3 respectively in SBI4. When these bits are set to 0 the respective SPE in SBI4 is disabled. When these bits are set to 1 the respective SPE in SBI4 is enabled. When an SPE is enabled each individual tributary within an SPE can be selectively enabled via the Extract Tributary RAM Indirect Access Control Data register. These bits must be written in a second write after the SPE*_TYP[2:0] bits have been set. SPE1_TYP[2:0], SPE2_TYP[2:0], SPE3_TYP[2:0]: SPE1_TYP[2:0], SPE2_TYP[2:0] and SPE3_TYP[2:0] select the SPE type for the three SPEs within SBI4 respectively. The types for each SPE are independently configured with possible types being T1, E1, DS3 or Fractional Rate. The settings for SPEx_TYP[2:0] are:
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Table 32
- SBI EXTRACT SPE_TYP[2:0] SPEx_TYP[2:0] X00 X01 010 011 11X Payload Type 28 T1/J1 links 21 E1links Single DS3 Link Unused Fractional Rate
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Register 0x600H: TAPI Control Register Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 To Bit 6 Bit 5 Bit 4 Bit 3 To Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W Type Function Unused Default X
ENABLE Reserved Reserved Unused
0 0 0 X
ANYPHYL MODE Unused
0 0 X
CSCOMODE
0
The Control Register is used to set TAPI-12 mode. The Control Register is also used to enable the TAPI-12. CSCOMODE: The mode bit (CSCOMODE) is used to disable TPA masking that occurs when data on a channel is being received at the same time this channel is being polled. When CSCOMODE=1, masking is disabled. MODE: The mode bit (MODE) is used to configure operating modes of TAPI-12. When MODE is set low, TAPI-12 operates in non-blocking mode; that is, TAPI-12 will only deassert TRDY if it cannot accept 64 bytes (1 FIFO block) of data. When MODE is set high, TAPI-12 operates in blocking mode; that is, TAPI-12 will deassert TRDY if the free space in the circular FIFO is less than the data transfer burst length when TSX is sampled high. This bit should always be set to a 1 for guaranteed operation.
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ANYPHYL: The ANY PHY Level select bit allows selection between ANY PHY L2 and ANY PHY L3. Table 33 - ANY-PHY Encoding ANY-PHY 0 1 ANY-PHY Level Level 2 Level 3
Reserved: The reserved bits must be set low for correct operation of the FREEDM336A1024 device ENABLE: The Enable bit (ENABLE) enables normal operation of the TAPI-12. When ENABLE is set low, the TAPI-12 will complete the current data transfer and will respond to any further transactions on the APPI normally (by setting TRDY high), but will ignore any data. When ENABLE is set high, the TAPI-12 operates normally.
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Register 0x604 : TAPI Indirect Channel Provisioning Register Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 To Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Type Function Unused Default X
BUSY RWB Unused
X 0 X
CHAN[9] CHAN[8] CHAN[7] CHAN[6] CHAN[5] CHAN[4] CHAN[3] CHAN[2] CHAN[1] CHAN[0]
0 0 0 0 0 0 0 0 0 0
The Indirect Channel Provisioning Register provides the channel number used to access the TAPI-12 channel provisioning RAM. Writing to this register triggers an indirect channel register access. CHAN[9:0]: The indirect channel number bits (CHAN[9:0]) indicate the channel to be configured or interrogated in the indirect access. RWB: The Read/Write Bar (RWB) bit selects between a provisioning/unprovisioning operation (write) or a query operation (read). Writing a logic 0 to RWB triggers the provisioning or unprovisioning of the channel specified by CHAN[9:0]. Writing a logic 1 to RWB triggers a query of the channel specified by CHAN[9:0].
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BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available or to determine when a new indirect write operation may commence.
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Register 0x608 : TAPI Indirect Channel Data Register Bit Bit 31 To Bit 16 Bit 15 Bit 14 To Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
PROV Unused
0 X
BLEN[7] BLEN[6] BLEN[5] BLEN[4] BLEN[3] BLEN[2] BLEN[1] BLEN[0]
X X X X X X X X
The TAPI Indirect Channel Data Register contains data read from the TAPI-12 channel provision RAM after an indirect read operation or data to be written to channel provision RAM in an indirect write operation. BLEN[7:0]: The channel burst length (BLEN[7:0]) bits report the data transfer burst length read from the TAPI-12 channel provision RAM after an indirect read operation has completed. The data transfer burst length specifies the length (in bytes, less one) of burst data transfers on the transmit APPI that are not terminated by the assertion of TEOP. The data transfer burst length can be specified on a per-channel basis. The data transfer burst length to be written to the channel provision RAM in an indirect write operation must be set up in this register before triggering the write. BLEN[7:0] reflects the value written until the completion of a subsequent indirect read operation. The following values of BLEN[7:0] are valid:
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Table 34
- Valid BLEN BLEN[7:0] 00111111 01111111 11111111 APPI transfer burst length 64 128 256
PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the TAPI-12 channel provision RAM after an indirect read operation has completed. The provision enable flag to be written to the TAPI12 channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the channel as indicated by CHAN[9:0] is provisioned. When PROV is set low, the channel indicated by CHAN[9:0] is unprovisioned. PROV reflects the value written until the completion of a subsequent indirect read operation. Traffic to the Freedm-336A1024 must be stopped on a channel before that channel is unprovisioned.
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Register 0x60C: TAPI Reserved Register Bit Bit 31 To Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: The reserved bits must be left at their default value or set to 28H for correct operation of the FREEDM-336A1024 device. R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0 1 0 1 0 0 0
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Register 0x610: TAPI Status Register Bit Bit 31 To Bit 2 Bit 1 R Type Function Unused Default X
UNTSX
0
Bit 0 R FULL 0 The Status Register contains flag bits reflecting the current status of TAPI-12. This register does not remain set when the condition is not present. FULL: The full bit (FULL) reports the instantaneous full status of the circular FIFO. It is set high when free space in the circular FIFO is smaller than a complete data segment and TSX is sampled high. When the full bit is high, it shows that the reader controller has not been able to empty the circular FIFO fast enough to keep pace with the writer controller. When TAPI-12 operates in non-blocking mode, the writer controller risks overflowing the circular FIFO when the full bit is set high. UNTSX: The unexpected TSX bit (UNTSX) reports instantaneous events when TSX is sampled high in an unexpected location. When TAPI-12 operates in blocking mode, UNTSX is set high when TSX is sampled high and the writer controller has only received less data than specified in the channel provision RAM, while TEOP has not been asserted for the current data transfer. When TAPI12 operates in non-blocking mode, UNTSX is set high when TSX is sampled high in a location violating the minimum TSX gap for packets smaller than 40 bytes; UNTSX is also set high when TSX is sampled high and the writer controller has only received data with a size that is less than specified in the channel provision RAM but larger than 40 bytes, while TEOP has not been asserted for the current data transfer.
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Register 0x614: TAPI Base Address Register Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
BADDR[15] BADDR[14] BADDR[13] BADDR[12] BADDR[11] BADDR[10] BADDR[9] BADDR[8] BADDR[7] BADDR[6] BADDR[5] BADDR[4] BADDR[3] BADDR[2] BADDR[1] BADDR[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The Base Address Register specifies the minimum valid ANY-PHY channel address for TAPI-12. BADDR[15:0]: The base address bits (BADDR[15:0]) specifies the minimum valid ANY-PHY channel address residing in TAPI-12. A channel prepend address provided on TXDATA or a polling address provided on TXADDR is deemed out of range if it is greater than the sum of RADDR[15:0] and BADDR[15:0] or less than BADDR[15:0]. BADDR[15:0] must be a multiple of RADDR[15:0]+1 (see TAPI Range Address Register).
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Register 0x618: TAPI Range Address Register Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
RADDR[15] RADDR[14] RADDR[13] RADDR[12] RADDR[11] RADDR[10] RADDR[9] RADDR[8] RADDR[7] RADDR[6] RADDR[5] RADDR[4] RADDR[3] RADDR[2] RADDR[1] RADDR[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The Range Address Register specifies the valid range of ANY-PHY channel address for TAPI-12. RADDR[15:0]: The range address bits (RADDR[15:0]) specifies the (valid range-1) of ANYPHY channel address residing in TAPI-12. A channel prepend address provided on TXDATA or a polling address on TXADDR is deemed out of range if it is greater than the sum of RADDR[15:0] and BADDR[15:0] or less than BADDR[15:0] but must be rounded to a power of 2 - 1. I.e.. For a range of 672 or 1024 channels, RADDR[15:0] must be set to the value 0000001111111111.
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Register 0x680 : SBI INSERT Control Bit Bit 31 To Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type Function Unused Default X
Reserved Reserved Reserved SBI_PAR_CTL
0 0 0 1
This register controls the operation of the SBI INSERT block. SBI_PAR_CTL The SBI_PAR_CTL bit is used to configure the Parity mode for generation of the SBI parity signal, ADP as follows: When SBI_PAR_CTL is '0' parity is even. When SBI_PAR_CTL is `1' parity is odd. Reserved: The reserved bits must be set low for correct operation of the FREEDM336A1024 device.
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Register 0x68C : SBI INSERT T1 Frame Pulse Offset Register Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Function Unused Unused Unused Reserved OFFSET_T1[11] OFFSET_T1[10] OFFSET_T1[9] OFFSET_T1[8] OFFSET_T1[7] OFFSET_T1[6] OFFSET_T1[5] OFFSET_T1[4] OFFSET_T1[3] OFFSET_T1[2] OFFSET_T1[1] OFFSET_T1[0] Default 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0
This register controls the T1 Frame pulse offset. OFFSET_T1[11:0]: This parameter must be programmed to OFFSET T1[11:0] = 1400 (decimal) or 0101 0111 1000 (binary) for correct operation of the device. Reserved: * The reserved bit must be left high for correct operation of the FREEDM336A1024 device.
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Register 0x690 : SBI INSERT E1 Frame Pulse Offset Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Function Unused Unused Unused Reserved OFFSET_E1[11] OFFSET_E1[10] OFFSET_E1[9] OFFSET_E1[8] OFFSET_E1[7] OFFSET_E1[6] OFFSET_E1[5] OFFSET_E1[4] OFFSET_E1[3] OFFSET_E1[2] OFFSET_E1[1] OFFSET_E1[0] Default 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0
This register controls the E1 Frame pulse offset. OFFSET_E1[11:0]: This parameter must be programmed to OFFSET E1[11:0] = 1654 (decimal) or 0110 0111 0110 (binary) for correct operation of the device. Reserved: * The reserved bit must be set low for correct operation of the FREEDM336A1024 device.
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Register 0x694 : SBI INSERT Tributary Indirect Access Address Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused Default X
BUSY RWB Reserved Reserved Unused Reserved SBI[2] SBI[1] SBI[0] SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0]
0 0 0 0 X 0 0 0 0 0 0 0 0 0 0 0
This register provides the transmit SPE and link number used to access the SBI INSERT tributary control configuration RAM. TRIB[4:0], SPE[1:0] and SBI[2:0]: The TRIB[4:0], SPE[1:0] and SBI[2:0] fields are used to fully specify to which SBI tributary the Control register write or read operation will apply. TRIB[4:0] specifies the SBI tributary number within the SBI/SPE as specified by the SPE[1:0] and SBI[2:0] fields. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Legal values for SBI[2:0] are b'001' through b`100'.
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Reserved: The reserved bit must be set low for correct operation of the FREEDM336A1024 device. RWB The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the tributary control configuration RAM. Writing a `0' to RWB triggers an indirect write operation. Data to be written is taken from the SBI INSERT Tributary Indirect Access Data Register. Writing a `1' to RWB triggers an indirect read operation. The data read can be found in the SBI INSERT Control Tributary RAM Indirect Access Data Register. BUSY The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when a write to the SBI INSERT Tributary Indirect Access Address Register triggers an indirect access and will stay high until the access is complete. This register should be polled to determine when data from an indirect read operation is available in the SBI INSERT Tributary Indirect Access Data Register or to determine when a new indirect write operation may commence.
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Register 0x69C : SBI INSERT Tributary Indirect Access Data Bit Bit 31 To Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W SBIIP_LB SYNCH_TRIB CLK_MSTR TRIB_TYP[1] TRIB_TYP[0] Reserved ENBL 0 0 0 0 0 0 0 Type Function Unused Default X
This register contains data read from the SBI INSERT tributary control configuration RAM after an indirect read operation or data to be written to the tributary control configuration RAM in an indirect write operation. ENBL The ENBL bit is used to enable the Tributary. Writing to an Insert Tributary Control and Status RAM location with the ENBL bit set enables the INSBI to take tributary data from an SBIIP link and transmit that data to the SBI tributary for that link. Reserved: The reserved bit must be set low for correct operation of the FREEDM336A1024 device. TRIB_TYP[1:0] The TRIB_TYP[1:0] field is used to specify the characteristics of the SBI tributary as shown in Table 35 below:
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Table 35
- TRIB_TYP Encoding TRIB_TYP[1:0] 00 01 10 11 Tributary type Reserved Framed Unframed Reserved
CLK_MSTR The CLK_MSTR bit configures the SBI tributary to operate as a timing master or slave. Setting CLK_MSTR to 1 configures the tributary as a timing master (AJUST_REQ input ignored). Setting CLK_MSTR to 0 configures the tributary as a timing slave (requests on AJUST_REQ honored). SYNCH_TRIB: The SYNCH_TRIB bit is used to indicate whether the tributary is locked to the SBI SPE (i.e. is in synchronous mode). If this bit is set then the tributary is locked. If this bit is not set, then the tributary is free to float. This bit will default to off. SBIIP_LB: The SBIIP loopback bit selects the SBIIP extract loopback bus as the source for this tributary. When SBIIP_LB is set to 1 LB_EXT_DATA, LB_EXT_LINKRATE, etc. are used as the input data stream for the selected tributary. When SBIIP_LB is set to 0 the insert SBIIP bus is the source for the selected tributary. Loopbacks are only possible with floating tributaries, i.e. can not be used with synchronous T1 and E1 tributaries. Note: Any write to a Tributary Control RAM location for a tributary will generate a configuration reset on that tributary, irrespective of whether the data written to the tributary control RAM location is unchanged from the previous value.
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Register 0x6A0: SBI INSERT SBI1 SPE Configuration Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SPE3_EN SPE3_TYP[2] SPE3_TYP [1] SPE3_TYP [0] SPE2_EN SPE2_TYP[2] SPE2_TYP [1] SPE2_TYP [0] SPE1_EN SPE1_TYP[2] SPE1_TYP [1] SPE1_TYP [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type R Function Unused Default 0
SPE1_EN, SPE2_EN, SPE3_EN: Enables SPE1, SPE2 and SPE3 respectively in SBI1. When these bits are set to 0 the respective SPE in SBI1 is disabled. When these bits are set to 1 the respective SPE in SBI1 is enabled. When an SPE is enabled each individual tributary within an SPE can be selectively enabled via the Insert Tributary Control Indirect Access Data register. SPE1_TYP[2:0], SPE2_TYP[2:0], SPE3_TYP[2:0]: SPE1_TYP[2:0], SPE2_TYP[2:0] and SPE3_TYP[2:0] select the SPE type for the three SPEs within SBI1 respectively. The types for each SPE are independently configured with possible types being T1, E1, DS3 or Fractional Rate. The settings for SPEx_TYP[2:0] are: Table 36 - SBI INSERT SPE_TYP[2:0] Payload Type
SPEx_TYP[2:0]
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X00 X01 010 011 11x
28 T1/J1 Links 21 E1 Links Single DS-3 Link Reserved Fractional Rate
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Register 0x6A4: SBI INSERT SBI2 SPE Configuration Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SPE3_EN SPE3_TYP[2] SPE3_TYP [1] SPE3_TYP [0] SPE2_EN SPE2_TYP[2] SPE2_TYP [1] SPE2_TYP [0] SPE1_EN SPE1_TYP[2] SPE1_TYP [1] SPE1_TYP [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type R Function Unused Default 0
SPE1_EN, SPE2_EN, SPE3_EN: Enables SPE1, SPE2 and SPE3 respectively in SBI1. When these bits are set to 0 the respective SPE in SBI1 is disabled. When these bits are set to 1 the respective SPE in SBI1 is enabled. When an SPE is enabled each individual tributary within an SPE can be selectively enabled via the Insert Tributary Control Indirect Access Data register. SPE1_TYP[2:0], SPE2_TYP[2:0], SPE3_TYP[2:0]: SPE1_TYP[2:0], SPE2_TYP[2:0] and SPE3_TYP[2:0] select the SPE type for the three SPEs within SBI2 respectively. The types for each SPE are independently configured with possible types being T1, E1, DS3 or Fractional Rate. The settings for SPEx_TYP[2:0] are: Table 37 - SBI INSERT SPE_TYP[2:0] Payload Type
SPEx_TYP[2:0]
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X00 X01 010 011 11x
28 T1/J1 Links 21 E1 Links Single DS-3 Link Reserved Fractional Rate
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Register 0x6A8: SBI INSERT SBI3 SPE Configuration Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SPE3_EN SPE3_TYP[2] SPE3_TYP [1] SPE3_TYP [0] SPE2_EN SPE2_TYP[2] SPE2_TYP [1] SPE2_TYP [0] SPE1_EN SPE1_TYP[2] SPE1_TYP [1] SPE1_TYP [0] 0 0 0 0 0 0 0 0 0 0 0 0 Type R Function Unused Default 0
SPE1_EN, SPE2_EN, SPE3_EN: Enables SPE1, SPE2 and SPE3 respectively in SBI1. When these bits are set to 0 the respective SPE in SBI1 is disabled. When these bits are set to 1 the respective SPE in SBI1 is enabled. When an SPE is enabled each individual tributary within an SPE can be selectively enabled via the Insert Tributary Control Indirect Access Data register. SPE1_TYP[2:0], SPE2_TYP[2:0], SPE3_TYP[2:0]: SPE1_TYP[2:0], SPE2_TYP[2:0] and SPE3_TYP[2:0] select the SPE type for the three SPEs within SBI2 respectively. The types for each SPE are independently configured with possible types being T1, E1, DS3 or Fractional Rate. The settings for SPEx_TYP[2:0] are: Table 38 - SBI INSERT SPE_TYP[2:0] Payload Type
SPEx_TYP[2:0]
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X00 X01 010 011 11x
28 T1/J1 Links 21 E1 Links Single DS-3 Link Reserved Fractional Rate
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Register 0x6AC: SBI INSERT SBI4 SPE Configuration Register Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R Function Unused Default 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
SPE3_EN SPE3_TYP[2] SPE3_TYP [1] SPE3_TYP [0] SPE2_EN SPE2_TYP[2] SPE2_TYP [1] SPE2_TYP [0] SPE1_EN SPE1_TYP[2] SPE1_TYP [1] SPE1_TYP [0]
0 0 0 0 0 0 0 0 0 0 0 0
SPE1_EN, SPE2_EN, SPE3_EN: Enables SPE1, SPE2 and SPE3 respectively in SBI1. When these bits are set to 0 the respective SPE in SBI1 is disabled. When these bits are set to 1 the respective SPE in SBI1 is enabled. When an SPE is enabled each individual tributary within an SPE can be selectively enabled via the Insert Tributary Control Indirect Access Data register. SPE1_TYP[2:0], SPE2_TYP[2:0], SPE3_TYP[2:0]: SPE1_TYP[2:0], SPE2_TYP[2:0] and SPE3_TYP[2:0] select the SPE type for the three SPEs within SBI4 respectively. The types for each SPE are independently configured with possible types being T1, E1, DS3 or Fractional Rate. The settings for SPEx_TYP[2:0] are:
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Table 39
- SBI INSERT SPE_TYP[2:0] Payload Type 28 T1/J1 Links 21 E1 Links Single DS-3 Link Reserved Fractional Rate X00 X01 010 011 11x
SPEx_TYP[2:0]
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Register 0x800: Memory Port Control Bit Bit 31 Bit 30 To Bit 29 Bit 28 To Bit 27 Bit 26 To Bit 24 Bit 23 To Bit 0 Writes to this register will start a BUMP2 access to the internal aperture defined by MPMemSelect. The completion of one access is signaled by BUMP2 asserting MPBusy to state low. During an internal access, while MPBusy is high, all BUMP2 Control Registers are accessible by the microprocessor. MPQuadAddr[23:0] Indicates the beginning quad long word address for the operation in memory. Up to 96 megabytes of memory is supported in each aperture by this address (or 4M 16-byte or 24-byte regions). For Chunk Buffer DRAM accesses, only even number addresses are valid. MPMemSelect[2:0] Selects the memory aperture. The aperture is chosen according to the following table. R/W MPQuadAddr[23:0] 0 R/W MPMemSelect[2:0] 0 R/W MPBurstLength[1:0] 0 Type R R/W Function MPBusy MPCommand[1:0] Default 0 0
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Table 40
- MPMEMSelect Function Aperture Selected Connection Context SRAM Chunk Buffer DRAM Resequencing DRAM Statistics Counters EQM-12 Memory TFRAG ANY-PHY Channel RAM RFRAG Memory Unused
MPMemSelect[2:0] 000 001 010 011 100 101 110 111 MPBurstLength[1:0]
Indicates how many long words of data will be written to or read from memory in one burst access. Data read from the memory goes to the Memory Read Data N registers. After a burst of 1 word only the Memory Read Data 1 register is updated, a burst of two words will update this register and Memory Read Data 2, and so on for bursts of 3 and 4 words. Similarly for write bursts when data from the Memory Write Data registers is written to the memory. Table 41 - MPBurstLength Function Long Words Selected 1 2 3 4
MPBurstLength[1:0] 00 01 10 11
For accesses to the Chunk Buffer DRAM, only the values 01 and 11 are valid. For accesses to the TFRAG ANY-PHY Channel RAM and the RFRAG RAM only the value of 00 is valid. MPCommand[1:0] Selects the type of access.
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Table 42
- MPCommand functions Command Selected Reserved Write Read Unused
MPCommand[1:0] 00 01 10 11 MPBusy
When a command is executed, this bit will automatically be set to a 1. When the command is complete, this bit will be cleared to zero. This signal is the inverse of MPISTATI found in the Interrupt Status Register.
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Register 0x804-0x810: Memory Write Data N, N=0..3 (Burstable) Bit Bit 31 To Bit 0 Writes to these registers are not allowed while MPBusy is active high and MPCommand[1:0]="01" (write). MPWrDataN[31:0], N = 0..3 The least significant 32 bits of write data to be directed to the address and aperture as specified in the memory port control register. Type R/W Function MPWrDataN[31:0] Default 0
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Register 0x814: Memory Write Data Overflow 1 (Burstable) Bit Bit 31 To Bit 16 Bit 15 To Bit 0 Writes to this register are not allowed while MPBusy is active high and MPCommand[1:0]="01" (write).This register is only used for writes to the Chunk Buffer Memory. MPWrData0[47:32] The most significant 16 bits of MPWrData0. MPWrData1[47:32] The most significant 16 bits of MPWrData1. R/W MPWrData0[47:32] 0 Type R/W Function MPWrData1[47:32] Default 0
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Register 0x818: Memory Write Data Overflow 2 (Burstable) Bit Bit 31 To Bit 16 Bit 15 To Bit 0 Writes to this register are not allowed while MPBusy is active high and MPCommand[1:0]="01" (write).This register is only used for writes to the Chunk Buffer Memory. MPWrData2[47:32] The most significant 16 bits of MPWrData2. MPWrData3[47:32] The most significant 16 bits of MPWrData3. R/W MPWrData2[47:32] 0 Type R/W Function MPWrData3[47:32] Default 0
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Register 0x81C-0x828: Memory Read Data N, N=0..3 (Burstable) Bit Bit 31 To Bit 0 When a read command (MPCommand[1:0]="10") is asserted, the data in these registers will be valid after MPBusy goes low and will stay valid until the end of the next read command. MPRdDataN[31:0], N = 0..3 The least significant 32 bits of read data from the address and aperture as specified in the memory port control register. MPRdDataN corresponds to MPLWordEn[N]. Type R Function MPRdDataN[31:0] Default 0
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Register 0x82C: Memory Read Data Overflow 1 (Burstable) Bit Bit 31 To Bit 16 Bit 15 To Bit 0 When a read command (MPCommand[1:0]="10") is asserted, the data in this register will be valid after MPBusy goes low and will stay valid until the end of the next read command. This register is only updated after reads from the Chunk buffer memory. MPRdData0[47:32] Indicates the most significant 16 bits of the first word of read data from memory. MPRdData1[47:32] Indicates the most significant 16 bits of the second word of read data from memory. R MPRdData0[47:32] 0 Type R Function MPRdData1[47:32] Default 0
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Register 0x830: Memory Read Data Overflow 2 (Burstable) Bit Bit 31 To Bit 16 Bit 15 To Bit 0 When a read command (MPCommand[1:0]="10") is asserted, the data in this register will be valid after MPBusy goes low and will stay valid until the end of the next read command. This register is only updated after reads from the Chunk Buffer Memory. MPRdData2[47:32] Indicates the most significant 16 bits of the third word of read data from memory. MPRdData3[47:32] Indicates the most significant 16 bits of the fourth word of read data from memory. R MPRdData2[47:32] 0 Type R Function MPRdData3[47:32] Default 0
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Register 0x884: Unexpected SN CI (USNCI) Bit Bit 31 To Bit 14 Bit 13 To Bit 0 CI The Connection Identifier (CI) of the connection that last experienced an unexpected SN. R/W CI 0 Type Function Unused Default X
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Register 0x888: Lost SN CI (LSNCI) Bit Bit 31 To Bit 14 Bit 13 To Bit 0 CI The Connection Identifier (CI) of the connection that last experienced a lost sequenced datagram. R/W CI 0 Type Function Unused Default X
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Register 0x88C: SRAM Parity Error Address (SPERRADD) Bit Bit 31 To Bit 18 Bit 17 To Bit 0 SPERRADD The last SRAM Address that was being accessed when a parity error occurred. R/W SPERRADD 0 Type Function Unused Default X
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Register 0x890: Excessive number of Fragments CI (ENFCI) Bit Bit 31 To Bit 14 Bit 13 To Bit 0 CI The Connection Identifier (CI) of the last connection on which a frame/packet was received with an excessive number of fragments. Maximum acceptable limit of fragments per packet is 82. R/W CI 0 Type Function Unused Default X
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Register 0x900 CB_DRAMC Status and Control Register Bit Bit 31 To Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R Reserved DECC ECC_OFF FUNC_MODE FPP_INIT PROV_MODE SDRAM_INIT 0 0 0 0 0 0 1 Type Function UNUSED Default X
This register provides status information regarding the state of the CB_DRAMC. Only one of SDRAM_INIT, PROV_MODE or FUNC_MODE at any given time is allowed to be set "high" in this register. Unpredicted behavior may result otherwise. The ECC_OFF bit should be set to 1 prior to or at the same time FPP_INIT is set to 1 for hardware initialization of the FPP_FIFO. For microprocessor initialization, these bits should be set to 1 prior to the initialization process. SDRAM _INIT: Indicates that the initialization sequence of the Chunk Buffer SDRAMs is in progress. Since this sequence is executing immediately following power-up, this bit is set to "1" by default. This bit is automatically cleared when the SDRAM initialization procedure is completed. PROV_MODE: This bit is automatically set by the CB_DRAMC when it finishes executing the initialization sequence required by the SDRAMs. When set, this bit indicates that the CB_DRAMC is in "Provision" mode and only the microprocessor can perform memory transactions. This bit should be cleared by the microprocessor when all SDRAM transactions are complete. In addition, note that setting this bit while the CB_DRAMC is in "Functional Mode" (with FUNC_MODE set) will cause undetermined results.
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FPP_INIT: When set, this bit indicates that the DRAMC is in the process of initializing the Free Pool Pointer (FPP) FIFO residing in the Chunk Buffer. Two options exist for initializing the FPP FIFO: The first requires the microprocessor to set the FPP_INIT bit. This will prompt a CB_DRAMC based initialization procedure of the FIFO. The other method is to initialize the FPP FIFO by direct microprocessor accesses. In that case there is no need to set this bit. FUNC_MODE: When set, this bit indicates that the CB_DRAMC is in "Functional Mode", i.e., it is ready to perform access to the Chunk Buffer on behalf of the various functional units of the chip. When the Free Pool Pointer (FPP) FIFO is initialized by the CB_DRAMC this bit will be automatically set by the CB_DRAMC at the end of the FPP FIFO initialization procedure. Otherwise this bit needs to be set by the microprocessor (when it finishes initializing the FPP FIFO). ECC_OFF: Setting this bit turns ECC off. ECC will not be added or corrected. When using the microprocessor interface to access the SDRAMs, this bit must be set to 1. DECC: The diagnostic ECC bit (DECC) configures TFRAG to logically invert the ECC for diagnostic purposes. When DECC is a logic one, ECC generated will be inverted. When DECC is a logic zero, a correct ECC will be generated. Reserved: The reserved bit must be set low for correct operation of the FREEDM336A1024 device.
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Register 0x904 : CB_DRAMC_COECCE Register Bit Bit 31 To Bit 24 Bit 23 To Bit 0 Correctable ECC Error Register. This register stores the last address of the chunk or FPP that caused an ECC error that was corrected. COADDR[23:0]: It stores the address of the latest ECC error detected and corrected, (i.e., if two consecutive chunks read from the memory caused a correctable ECC error, only the address of the last chunk is kept). R/W COADDR[23:0] 0 Type Function Unused Default X
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Register 0x908 : CB_DRAMC_UNCOECCE Register Bit Bit 31 To Bit 24 Bit 23 To Bit 0 Uncorrectable ECC Error Register. This register stores the last address of the chunk or FPP that caused 2 ECC errors, one of which can not be corrected. UNCOADDR[23:0]: It stores the address of the latest uncorrectable ECC error, (i.e., if two consecutive chunks read from the memory caused an uncorrectable ECC error, only the address of the last chunk is kept). R/W
UNCOADDR[23:0]
Type
Function Unused
Default X
0
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Register 0x918 RS_DRAMC Status and Control Register Bit Bit 31 To Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R Reserved DECC ECC_OFF FUNC_MODE FPP_INIT PROV_MODE SDRAM_INIT 0 0 0 0 0 0 1 Type Function Unused Default X
This register provides status information regarding the state of the RS_DRAMC. Only one of SDRAM_INIT, PROV_MODE or FUNC_MODE at any given time is allowed to be set "high" in this register. Unpredicted behavior may result otherwise. The ECC_OFF bit should be set to 1 prior to or at the same time FPP_INIT is set to 1 for hardware initialization of the FPP_FIFO. For microprocessor initialization, these bits should be set to 1 prior to the initialization process.
SDRAM _INIT: Indicates that the initialization sequence of the Resequencing Buffer SDRAMs is in progress. Since this sequence is executing immediately following power-up, this bit is set to "1" by default. This bit is automatically cleared when the SDRAM initialization procedure is completed. PROV_MODE: This bit is automatically set by the RS_DRAMC when it finishes executing the initialization sequence required by the SDRAMs. When set, this bit indicates that the RS_DRAMC is in "Provision" mode and only the microprocessor can perform memory transactions. This bit should be cleared by the microprocessor when all SDRAM transactions are complete. In addition, note that setting this bit while the RS_DRAMC is in "Functional Mode" (with FUNC_MODE set) will cause undetermined results.
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FPP_INIT: When set, this bit indicates that the RS_DRAMC is in the process of initializing the Free Pool Pointer (FPP) FIFO used by the resequencing logic (realized in the Resequencing Buffer). Two options exist for initializing the FPP FIFO: The first requires the microprocessor to set the FPP_INIT bit. This will prompt a RS_DRAMC based initialization procedure of the FIFO. The other method is to initialize the FPP FIFO by direct microprocessor accesses. In that case there is no need to set this bit. FUNC_MODE: When set, this bit indicates that the RS_DRAMC is in "Functional Mode", i.e., it is ready to perform accesses to the Resequencing Buffer. When the Free Pool Pointer (FPP) FIFO is initialized by the RS_DRAMC this bit will be automatically set by the RS_DRAMC at the end of the FPP FIFO initialization procedure. Otherwise this bit needs to be set by the microprocessor (when it finishes initializing the FPP FIFO). ECC_OFF: Setting this bit turns ECC off. ECC will not be added or corrected. When using the microprocessor interface to access the SDRAMs, this bit must be set to 1. DECC: The diagnostic ECC bit (DECC) configures DRAMC to logically invert the ECC for diagnostic purposes. When DECC is a logic one, ECC generated will be inverted. When DECC is a logic zero, a correct ECC will be generated. Reserved: The reserved bit must be set low for correct operation of the FREEDM336A1024 device.
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Register 0x91C : RS_DRAMC_COECCE Register Bit Bit 31 To Bit 24 Bit 23 To Bit 0 Correctable ECC Error Register. This register stores the last address that caused an ECC error that was corrected. COADDR[23:0]: It stores the address of the latest ECC error detected and corrected, (i.e., if two consecutive memory transactions caused a correctable ECC error, only the last address is kept). R/W COADDR[23:0] 0 Type Function Unused Default X
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Register 0x920 : RS_DRAMC_UNCOECCE Register Bit Bit 31 To Bit 24 Bit 23 To Bit 0 Uncorrectable ECC Error Register. This register stores the last address that caused 2 ECC errors, one of which can not be corrected. UNCOADDR[23:0]: It stores the address of the latest uncorrectable ECC error, (i.e., if two consecutive memory transactions caused an uncorrectable ECC error, only the last address is kept). R/W
UNCOADDR[23:0]
Type
Function Unused
Default X
0
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Register 0x9A0 : BIST Controller This control register is common to all BIST sequencers in the FREEDM336A1024.
Bit Bit 31 To Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type
Function Unused
Default X
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BISTPATTERN[7] BISTPATTERN[6] BISTPATTERN[5] BISTPATTERN[4] BISTPATTERN[3] BISTPATTERN[2] BISTPATTERN[1] BISTPATTERN[0] BISTMODE[2] BISTMODE[1] BISTMODE[0] BISTSIDE
0 0 0 0 0 0 0 0 1 0 0 0
The BIST Enable register must be set up prior to setup of this register. BISTSIDE: The BIST sequencer input BISTSIDE determines which port of dual-port RAMs is tested when the BIST logic is operating. BISTMODE[2:0]: The BIST sequencer input BISTMODE should be set to "010" to run BIST. Other values are reserved for use during PMC production test.
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BIST_PATTERN[7:0]: The BIST test data pattern that is applied to the RAMs during BIST.
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Register 0x9A4 : BIST Enable Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TAPI-12_EN RAPI-12_EN FRMBLD_EN EQM-12_EN IQM-12_EN CB_DRAMC_EN RS_DRAMC_EN TFRAG_EN RFRAG_EN PM-12_EN THDL-12_EN RHDL-12_EN TCAS-12_EN RCAS-12_EN INSBI336_EN EXSBI336_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
Each control bit in this register enables the BIST test of all memories controlled by the selected BIST sequencer. All memories in a selected block will be tested at the same time. It should be noted that for BIST to work, all clocks must be the same frequency (SYSCLK, RXCLK, TXCLK) and the maximum frequency of operation is 40 MHz. Of the BIST sequencers above, TAPI-12 and RAPI-12 are run off TXCLK and RXCLK respectively. All other BIST sequencers are run off SYSCLK. This feature is intended for production testing as opposed to on board testing. If this feature is desired for on board testing, the simplest solution is to set TAPI-12_EN and RAPI-12_EN to 0 (ie don't BIST test these memories) and set SYSCLK=52MHz.
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Register 0x9A8 : BIST Result Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R R R R R TAPI-12_RE RAPI-12_RE FRMBLD_RE EQM-12_RE IQM-12_RE CB_DRAMC_RE RS_DRAMC_RE TFRAG_RE RFRAG_RE PM-12_RE THDL-12_RE RHDL-12_RE TCAS-12_RE RCAS-12_RE INSBI336_RE EXSBI336_RE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
Each control bit in this register informs the result of the BIST test of all memories controlled by the selected BIST sequencer. An active high bit means that at least one of the tested memories in the specified block has an error. The reported result is only valid for bist sequencers that are enabled in the BIST Enable register, once the corresponding "End" bits in register 0x9AC become set..
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Register 0x9AC : BIST End Bit Bit 31 To Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R R R R R TAPI-12_ED RAPI-12_ED FRMBLD_ED EQM-12_ED IQM-12_ED CB_DRAMC_ED RS_DRAMC_ED TFRAG_ED RFRAG_ED PM-12_ED THDL-12_ED RHDL-12_ED TCAS-12_ED RCAS-12_ED INSBI336_ED EXSBI336_ED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type Function Unused Default X
Each control bit in this register informs the end of the BIST test of all memories controlled by the selected BIST sequencer.
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Register 0x9B0: EXSBI336 BIST ERROR Bit Bit 31 To Bit 8 Bit 7 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in EXSBI336 TSB. R ERRORN[7:0] 0 Type X Function Unused Default X
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Register 0x9B4: INSBI336 BIST ERROR Bit Bit 31 To Bit 10 Bit 9 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the INSBI336 TSB. R ERRORN[9:0] 0 Type X Function Unused Default X
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Register 0x9B8: RCAS-12 BIST ERROR Bit Bit 31 To Bit 3 Bit 2 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the RCAS-12 TSB. R ERRORN[2:0] 0 Type X Function Unused Default X
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Register 0x9BC: TCAS-12 BIST ERROR Bit Bit 31 To Bit 4 Bit 3 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the TCAS-12 TSB. R ERRORN[3:0] 0 Type X Function Unused Default X
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Register 0x9C0: RHDL-12 BIST ERROR Bit Bit 31 To Bit 21 Bit 20 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the RHDL-12 TSB. R ERRORN[20:0] 0 Type X Function Unused Default X
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Register 0x9C4: THDL-12 BIST ERROR Bit Bit 31 To Bit 22 Bit 21 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the THDL-12 TSB. R ERRORN[21:0] 0 Type X Function Unused Default X
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Register 0x9C8: PM-12 BIST ERROR Bit Bit 31 To Bit 6 Bit 5 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the PM12 TSB. R ERRORN[5:0] 0 Type X Function Unused Default X
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Register 0x9CC: RFRAG BIST ERROR Bit Bit 31 To Bit 3 Bit 2 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the RFRAG TSB. R ERRORN[2:0] 0 Type X Function Unused Default X
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Register 0x9D0: TFRAG BIST ERROR Bit Bit 31 To Bit 4 Bit 3 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the TFRAG TSB. R ERRORN[3:0] 0 Type X Function Unused Default X
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Register 0x9D4: RS_DRAMC BIST ERROR Bit Bit 31 To Bit 1 Bit 0 R ERRORN[0] 0 Type X Function Unused Default X
Each of these bits reports a possible error in one of the internal RAMs in the RS_DRAMC TSB.
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Register 0x9D8: CB_DRAMC BIST ERROR Bit Bit 31 To Bit 2 Bit 1 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the CB_DRAMC TSB. R ERRORN[1:0] 0 Type X Function Unused Default X
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Register 0x9DC: IQM-12 BIST ERROR Bit Bit 31 To Bit 5 Bit 4 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the IQM-12 TSB. R ERRORN[4:0] 0 Type X Function Unused Default X
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Register 0x9E0: EQM-12 BIST ERROR Bit Bit 31 To Bit 6 Bit 5 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the EQM-12 TSB. R ERRORN[5:0] 0 Type X Function Unused Default X
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Register 0x9E4: FRMBLD BIST ERROR Bit Bit 31 To Bit 3 Bit 2 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the FRMBLD TSB. R ERRORN[2:0] 0 Type X Function Unused Default X
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Register 0x9E8: RAPI-12 BIST ERROR Bit Bit 31 To Bit 2 Bit 1 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the RAPI-12 TSB. R ERRORN[1:0] 0 Type X Function Unused Default X
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Register 0x9EC: TAPI-12 BIST ERROR Bit Bit 31 To Bit 3 Bit 2 To Bit 0 Each of these bits reports a possible error in one of the internal RAMs in the TAPI-12 TSB. R ERRORN[2:0] 0 Type X Function Unused Default X
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11.2 Microprocessor accessible Memories Certain regions of the internal and external memories are used to configure and monitor the operation of the FREEDM-336A1024. Unlike the Normal Mode registers, these entries are not cleared upon read unless specified. Specified setups are required for correct operation of the chip. The default value for these memory bits is X unless specified. 11.2.1 PM-12 Memory Map This internal memory is used for storing statistics counters. This memory is accessed through the Memory Port Control register and is burst accessible. This memory is initialized to 0 on reset although on start up, small erred packets may pass through the chip causing the counts to be non-zero. The contents of the memory must be read every 2 seconds in order to ensure counters do not overflow. Counters will be reset to 0 once read. If the counter is allowed to overflow, it will not rollover but will hold the maximum count value until read. note1: Byte count includes 2-bytes per event for the CI prepend. Byte count (not including CI prepend) can be determined using corresponding event count. note2: Byte count includes 2-bytes per frame/packet for the error CI prepend.
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Table 43 Address
0000 RX_HDLC_CH (1K) 03FF 0400 RX_HDLC_CH (1K) 07FF 0800 RX_HDLC_CH (1K) 0BFF 0C00
- PM-12 Memory Map Record
Unused RX_BYTE_CNT
Bits 31:26 25:0
Description X Rx byte count per HDLC channel
Unused RX_PKT_CNT
31:26 25:0
X Rx packet count per HDLC channel
Unused RX_FRM_ABRT
31:26 25:0
X Rx framing aborts per HDLC channel
Unused RX_FCS_ERR_CNT
31:26 25:17 16:8 7:0 31:26 25:0 31:26 25:0
X FCS error count per HDLC channel Rx packet length greater than maximum allowed Non-octet aligned frames per Rx HDLC channel X Rx small datagrams discarded byte count per HDLC channel X Rx Chunk Buffer allocation exceeded byte count per HDLC channel X
RX_HDLC_CH (1K)
RX_PKTL_GMAX RX_NON_OA_FRM
0FFF 1000 RX_HDLC_CH (1K) 13FF 1400 RX_HDLC_CH (1K) 17FF 1800 RX_HDLC_CH (1K) 1BFF
Unused RX_SDD_BYTE_CNT
Unused RX_CBE_BYTE_CNT
Unused
31:26
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RX_SDD_EV
1C00 RX_HDLC_CH (1K) 1FFF 2000 TX_HDLC_CH (1K) 23FF 2400 TX_HDLC_CH (1K) 27FF 2800 TX_HDLC_CH (1K)
25:0 31:26 25:0
Unused RX_CBE_EV
Rx small datagrams discarded events per HDLC channel X Rx Chunk Buffer allocation exceeded events per HDLC channel X Tx byte count per HDLC channel X Tx packet count per HDLC channel
Unused TX_BYTE_CNT
31:26 25:0 31:26 25:0
Unused TX_PKT_CNT
Unused
31:26
X
2BFF 2C00 2C01 2C02 2C03 2C04 2C05
TX_FRM_ABRT RX_FIFO_OF RX_UNEXP_SQNUM RX_FCS_BYTE_CNT RX_NOA_BYTE_CNT RX_FOF_BYTE_CNT RX_GMX_BYTE_CNT
25:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0
Tx framing aborts per HDLC channel Rx FIFO overflow Rx unexpected sequence number events Rx byte count of datagrams with FCS errors*note1 Rx byte count of non-octet aligned datagrams*note1 Rx byte count of datagrams with channel FIFO overflow errors*note1 Rx byte count of datagrams with packet length greater than maximum allowed*note1 Rx byte count of datagrams with unexpected sequence number*note1
2C06
RX_FOR_BYTE_CNT
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2C07 2C08 2C09 2C0A 2C0B 2C0C 2C0D-2C13
RX_ABR_BYTE_CNT RX_UHF_BYTE_CNT RX_LOST_EV RX_PKLT_LMIN RX_EXC_FR_NBR TX_FIFO_UF Reserved
31:0 31:0 31:0 31:0 31:0 31:0 31:0
Rx byte count of datagrams with abort errors*note1 Rx byte count of datagrams with unsupported header format*note2 Rx lost SN events Rx packet length less than minimum allowed Rx excessive number of fragments events Tx FIFO underflow X
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11.2.2 EQM-12 Memory This internal memory is used to setup configuration and read status per Egress HDLC Channel and Multigroup. The default value of this memory is 0. All Reserved bits must be set to the value defined for correct operation. Table 44 Address 000 - EQM-12 Memory Map Word:Bits 127:122 121 120:102 Description X Reserved. Must be set to 0 for correct operation. Space threshold. Must be setup to control HDLC Channel availability indications over the ANY PHY I/F. SPC_THR multiplied by 32 represents the maximum number of bytes below which and HDLC channel will indicate that it has space to accept a new datagram. SPC_THR should be set to: OV_THR - MRU/32 Reserved. Must be set to 0 for correct operation. Overflow Threshold. This value must be set larger than the SPC_THR value to indicate at which point and overflow interrupt is generated. Multilink Group Number. ANY-PHY Channel number. Reserved. Must be set to 1 for correct operation. Reserved. Must be set to 0 for correct operation. Must be set for HDLC channels that belong to a multilink bundle. Reserved. Must be set to 0.
Record Unused Reserved SPC_THR[18:0]
HDLC_CH (1024) each address = 4x32bits Reserved OV_THR[18:0] 101 100:82
MLG[7:0] AP_CHAN[9:0] Reserved Reserved ML 3FF Reserved
81:74 73:64 63 62 61 60:0
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400
Unused Round Robin
199:195 194
ML_GRP Even Addresses = 4x32bits Odd Addresses = 2x32bits+8 bits
RR Start Index
193:190
Reserved ML_OV_THR[18: 0] Reserved ML_SPC_THR[18 :0] Reserved Reserved Reserved Unused NUM_HCH[3:0] HDLC_CHAN[119 :0]
189 188:170 169 168:150 149 148 147:128 127:124 123:120 119:0
54F
X Sets lowest fill queue arbitration to round robin mode. The lowest fill queue is always selected as the next HDLC channel to be serviced. When multiple queues contain the same number of bytes and Round Robin is set, priority is given to the HDLC channel in the group following the one that was just serviced. When set to 0, priority is always given to the lowest channel in the group with lowest fill. Round Robin starting index. This context indicates the channel in a ML group which will have highest priority if multiple channels have lowest fill. This index can be used to dictate which channel will first be used when a bundle is started up. Alternatively, this can be set to 0 and the first fragment will be sent down the first link in the bundle. Reserved. Must be set to 0 for correct operation. Multilink Overflow Threshold. Defined as above. This value overrides the HDLC channel threshold value. Reserved. Must be set to 0 for correct operation. Multilink Space Threshold. Defined as above. This value overrides the HDLC channel threshold value. Reserved. Must be set to 0 for correct operation. Reserved. Must be set to 1 for correct operation. Reserved. Must be set to 0 . X Number of HDLC channels in ML group. The multilink members (max of 12 HDLC channels). The first member is HDLC_CHAN[9:0] and the last member is HDLC_CHAN[119:110].
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11.2.3 TFRAG ANY-PHY Channel RAM Memory Map This internal memory must be written to setup Egress ANY PHY Channel configuration. The default value of this memory is 0. MPBurstLength[1:0] must = 00 for access to this memory. Table 45 Address 000 - TFRAG ANY-PHY Channel RAM Memory Map Bits 31:24 23 22 21:14 13 12:10 Description X. PID Compression enabled. Address/Control Compression enable. Multilink Group. This must be set to the Multilink bundle number. Does not apply if in Single Link Mode. 1 indicates that this channel is Multilink. Indicates data type as follows: 000 - PPP 001 -FR 010 - Transparent Mode 011 - Unused 1XX - Unused The HDLC Channel for Single Link Mode. Does not apply if in Multilink Mode. X 1 - Enable detection of EOP Loss. If the ANY-PHY channel number changes before end-of-packet is received, the next segment will be interpreted as endof-packet. Reserved. Must be left at default or written to 0 for correct operation. X. Read only. X. Read only. X. Read only.
Record Unused PPP_PID_COMP PPP_ADDR_CTR L_COMP ML_GROUP[7:0] ML_CH DATA_TYPE[2:0]
ANY PHY CHANNEL # (1024)
HDLC_CHAN[9:0] 3FF 400 Unused DET_EOP_LOSS
9:0 31:2 1
Reserved 401 402 403 Reserved Reserved Reserved
0 31:0 31:0 31:0
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11.2.4 RFRAG Memory Map This internal memory must be written to setup Ingress HDLC Channel configuration. The default value of this memory is 0. MPBurstLength[1:0] must = 00 for access to this memory.
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Table 46 Address 000
- RFRAG Memory Map Bits 31:22 21 Description Must be written to 0 for correct operation. Small datagram discard threshold override. Set this bit to 1 to override the default 40byte small datagram discard threshold with the value programmed into the SDDSCRD_THR[5:0] register. Small datagram discard threshold. When the SDDSCRD_OVR control bit is set to 1, program this register to the byte size (0 to 56) under which small datagrams will be discarded when an excessive number of datagrams are waiting to be processed by the resequencing engine. Protocol definition. 00 - PPP 01 - Frame Relay 10 - Transparent Mode 11 - Unused Address-and-Control field compression. Set this bit to 1 to allow the reception of Address-and-Control field compressed PPP headers. Uncompressed headers may also be received when this bit is set, but must carry the standard 0xFF and 0x03 values. This control bit is only used in PPP mode. Protocol field compression. Set this bit to 1 to allow the reception of Protocol field compressed PPP headers. Uncompressed headers may also be received when this bit is set. This control bit is only used in PPP mode. Sequence number format. This control bit is only used in PPP mode. 0 - 12 bits 1 - 24 bits
Record Reserved SDDSCRD_OVR
SDDSCRD_THR [5:0]
20:15
PTCL_PPP [1:0] HDLC CHANNEL # ACF_CPRS (1024)
14:13
12
PF_CPRS
11
SEQFMT_12
10
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3FF
AP_CHAN [9:0]
9:0
400
Reserved AP_ALLOC_THR
31:23 22:4
ANY-PHY CHANNEL # (1024) OUTFMT_FRPK
AP_CIOUT
3 2
7FF
AP_SEGSIZE[1:0]
1:0
ANY-PHY channel number. Program this register to the ANY-PHY channel number associated with this HDLC Channel. Prior to tearing down an ANY-PHY channel, all CI's associated with that ANY_PHY channel must first be torn down following the specified tear down procedure. Must be written to 0 for correct operation. ANY-PHY storage allocation threshold. Program this register to the allowed number of chunks of storage above which datagrams received for this ANY-PHY channel will be discarded. Note that this threshold will be verified only at the start of every datagram (i.e., no datagram will be discarded if its first chunk was accepted, even though subsequent chunks may cause the ANY-PHY storage allocation threshold to be exceeded). Care must therefore be taken when defining ANY-PHY storage allocation thresholds to reserve (subtract) enough headroom for storage of one additional datagram. Output format (frame/packet or fragment). 0 - Frame/Packet 1 - Fragment ANY-PHY connection identifier output. Set this bit to 1 to indicate that the connection identifier is to be pre-pended to all datagram transfers across a downstream ANY-PHY interface. This bit will be overridden and forced to 1 when an erred datagram is received. This bit should never be cleared when sequenced datagrams are expected as this will cause an unexpected presence of sequence number error. Ingress ANY-PHY channel output segment size (64, 128, or 256 bytes). Each channel must be programmed with the same value. 00 - 64 bytes 01 - 128 bytes 10 - 256 bytes 11 - Unused
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800 BFF C00
AP_NCHNKS[18:0]
31:0 31:19 18:0
FFF
Reserved. Must be left at default or written to 0 for correct operation. Unused Number of chunks stored in external chunk buffer
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11.2.5 Re-Sequence Structures (RS) Memory Map This external memory can be read or written with any value for test purposes before Functional Mode (FUNC_MODE) in RS_DRAMC Status and Control Register is enabled. The contents of the memory must be left in the state described below for correct operation. ECC Protection can be enabled in RS_DRAMC Status and Control Register. If ECC is enabled, bits 31-24 are overwritten with the ECC value. If ECC is disabled, bits 31-24 are written with the data presented.
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Table 47 Address
- RS Memory Map Bits Description
Record
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000000
CI_LOOKUP
31:0 Connection Identifier Lookup record. This record must be
populated according to the record description below. All unused locations must be set to a default connection identifier. Whenever a connection is de-commissioned , the location must be written with a default connection identifier. A Unique CI must be used for each ANY-PHY channel. All CI's in an ANY-PHY channel must be torn down before an ANY-PHY channel is torn down. The connection Identifier lookup address is generated as follows: Bits 23:22 - 0 Bits 21:12 - HDLC CH number Bits 11:10 - 00 - Sequenced or Transparent Mode 01 - Non-sequenced 10 - Control (ML_FR, ML_PPP, SL_PPP) 11 - Corrupt Bits 9:0 - 0 for Corrupt, Control or Transparent Mode. DLCI or COS otherwise (although COS=0 if non-
(HDLC# x 4096 = 4M)
sequenced).
Sequenced CI lookup record consists of 1024 entries per HDLC channel. In frame relay 1024 unique DLCI numbers can be mapped to 1-to-1024 CI numbers. In PPP 16 COS numbers can be mapped to 1-to-16 CI numbers. For each sequenced connection in an HDLC bundle, the same CI must be set up for each HDLC#. See Table 48 for details. This format is also used for transparent mode operation but the only valid instances for bits 11:10 are 00 or 11 and address bits 9:0 must be set to 0. Non-sequenced CI lookup record consists of 1024 entries per HDLC channel. In frame relay 1024 unique DLCI numbers can be mapped to 1-to-1024 CI numbers. In PPP all channel numbers are mapped to 1 CI number. See Table 49 for details. Control CI lookup record consists of 1 entry per HDLC channel. In multilink frame relay an active control bit in the frame header results in an index to the CI present in this record In single or multilink PPP an active NCP or LCP bit in the packet header results in an index to the CI present in this record. For Single Link FR, control packets are identified by DLCI and these packets must be identified by putting a unique CI in the nonsequenced table based on DLCI. See Table 50 for details. Corrupt CI lookup record consists of 1 entry per HDLC channel. A datagram marked as corrupted will result in an index to the corrupt CI lookup record. See Table 51 for details.
3FFFFF
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400000 (256k) 43FFFF 440000 (3.75M) 7FFFFF 800000 (2M) 9FFFFF A00000 (512k entries x 2 locations per entry) AFFFFF B00000
Reserved
31:0 LSB Record Status. Upon initialization, S/W must write this field to 0 for correct operation of the chip.
Unused
31:0 X
Reserved
31:0 MSB Record. Upon initialization, S/W must write this field to 0 for correct operation of the chip.
Reserved
31:0 Used by hardware.
LSB_RCD _FREELIST
(32k-40h)
B07FBF B07FC0 (.96875M) BFFFFF C00000 (4M) FFFFFF
31:0 LSB Record Freelist record. Each entry points to the location an unoccupied LSB record with each LSB record comprising 128 address locations. When the RS_DRAMC status register bit FPP_INIT is set, internal logic writes a unique 15-bit pointer value to each of the 32k freelist locations (pointer values ranging from 40h to 7FFFh). If the RS_DRAMC status register bit FPP_INIT is not set, and has not been set since initialization of the device, then the microprocessor must populate the LSB record freelist as the internal logic will not have been invoked to do so. See Table 54 for details. 31:0 X
Unused
Reserved
31:0 Used by hardware.
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Table 48 Relative Address 000000 (1k) index via DLCI or COS number 0003FF
- Sequenced Connection Identifier Lookup Record bits 31:24 23:14 13:0 Description These bits are ignored and overwritten with an ECC value via logic within the device. X CI number ranging from 0d to 16,383d.
Record Reserved Unused CI_NUMBER
Table 49 Relative Address 000400 (1k) index via DLCI or COS number 0007FF
- Non-sequenced Connection Identification Lookup Record bits 31:24 23:14 13:0 Description These bits are ignored and overwritten with an ECC value via logic within the device. X CI number ranging from 0d to 16,383d.
Record Reserved Unused CI_NUMBER
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Table 50 Relative Address 000800 (1)
- Control Connection Identifier lookup record bits 31:24 23:14 13:0 Description These bits are ignored and overwritten with an ECC value via logic within the device. X CI number ranging from 0d to 16,383d.
Record Reserved Unused CI_NUMBER
Table 51 Relative Address 000C00 (1)
- Corrupt Connection Identifier Lookup record bits 31:24 23:14 13:0 Description These bits are ignored and overwritten with an ECC value via logic within the device. X CI number ranging from 0d to 16,383d.
Record Reserved Unused CI_NUMBER
Table 52 Address 400000h
-LSB Records Status record Bits 31:2 1 Description A repetition of bits 0 and 1 pairs for fifteen other LSB record locations. End bit. Valid only when the OCP_BIT is set. Holds the value of the End bit associated with the datagram information stored in the corresponding LSB record location. Occupied bit. Set to one when corresponding LSB record location is occupied with a valid datagram pointer and related information.
Record END_BIT/ OCP_BIT END_BIT
(256k) OCP_BIT 0
43FFFFh
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Table 53 Address 800000h (2M) 9FFFFFh
-MSB Records record Bits 31:24 23:16 15 14:0 Description ECC value X Pointer validation bit 15-bit pointer to one of the 32k LSB records
Record Reserved Unused VAL_PTR LSB_PTR
Table 54 Address B00000 (32k-40h) B07FBF
- LSB Record Freelist record Bits 31:24 23:15 14:0 Description These bits are ignored and overwritten with an ECC value via logic within the device. X 15-bit LSB record pointer to one of the 32k LSB records. Prior to device operation each location is to be populated with a unique number ranging from 40h to 7FFFh.
Record Reserved Unused LSB_RCD_PT R
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11.2.6 Chunk Buffer Memory Map This external memory can be read or written with any value for test purposes before Functional Mode (FUNC_MODE) is enabled in the CB_DRAMC Status and Control register. The contents of the memory must be left in the state described below for correct operation. Certain fields can be setup by H/W (also described below) if selected.
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Table 55 Address 000000 (4M) 3FFFFF 400000
- Chunk Buffer Memory Map (only even addresses are valid) Bits 47:0 47:0 Description X Ingress Free List Pointers. Each entry contains 2 x 48 bit words making up a 96 bit word. For S/W setup of the Free List Pointers, the record must be filled with the following data: 00400-7FFFF . I.e.. Address = 400000 Data = 0040016, 0040116,, 00000000002 0040216, 0040316,, 00000000002 **Address = 400002 Data = 0040416, 0040516,, 00000000002 0040616, 0040716,, 00000000002 Address = 400004 Data = 0040816, 0040916,, 00000000002 0040A16, 0040B16,, 00000000002 **Address = 400006 Data = 0040C16, 0040D16,, 00000000002 0040E16, 0040F16,, 00000000002 . . . Address = 43FDFC Data = 7FFF816, 7FFF916,, 00000000002 7FFFA16, 7FFFB16,, 00000000002 *****Address = 43FDFC Data = 7FFFC16, 7FFFD16,, 00000000002 7FFFE16, 7FFFF16,, 00000000002 Address = 43FE00-43FFFF Data = Leave at default value.
Record Reserved IN_FPP _STORE
(256K)
43FFFF 440000 7FFFFF 800000 (4M) BFFFFF Unused Reserved 47:0 47:0
This record can also be set up by h/w by setting the FPP_INIT bit in the CB_DRAM Status Register. X X
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C00000
EG_FPP _STORE
47:0
Egress Free List Pointers. Each entry contains 2 x 48 bit words making up a 96 bit word. For S/W setup of the Free List Pointers, the record must be filled with the following data: 00400-7FFFF . I.e.. Address = C00000 Data = 0002,040016 ,0002,040116,002,8 bit ECC 0002,040216 ,0002,040316,002,8 bit ECC **Address = C00002 Data = 0002,040416 ,0002,040516,002,8 bit ECC 0002,040616 ,0002,040716,002,8 bit ECC Address = C00004 Data = 0002,040816 ,0002,040916,002,8 bit ECC 0002,040A16 ,0002,040B16,002,8 bit ECC **Address = C00006 Data = 0002,040C16 ,0002,040D16,002,8 bit ECC 0002,040E16 ,0002,040F16,002,8 bit ECC . . . Address = C3FDFC Data = 1112,FFF816 ,1112,FFF916,002,8 bit ECC 1112,FFFA16 ,1112,FFFB16,002,8 bit ECC *****Address = C3FDFC Data = 1112,FFFC16 ,1112,FFFD16,002,8 bit ECC 1112,FFFE16 ,1112,FFFF16,002,8 bit ECC Address = C3FE00-C3FFFF Data = Leave at default value. This record can also be set up by h/w by setting the FPP_INIT bit in the CB_DRAM Status Register.
(256K)
C3FFFF
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C40000 FFFFFF
Unused
47:0
X
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11.2.7 Connection Context (CC) Memory Map This memory holds connection configuration for both Ingress (RX) and Egress (Tx). This external memory can be read or written with any value for test purposes before Traffic is enabled. The contents of the memory must be left in the state described below for correct operation. Each connection contains 16 32bit records (W15-W0). When writing to word 0 to set up a Rx connection, words 1-3 must also be written to the value 0. Addressing per CI is described as follows: Table 56 Address 00000 00001 ... 0000F 00010 00011 ... 0001F 3FFF0 3FFF1 ... 3FFFF - Connection Context Memory Addressing CI # 0000 0000 ... 0000 0001 0001 ... 0001 3FFF 3FFF ... 3FFF Word W0 W1 ... W15 W0 W1 ... W15 W0 W1 ... W15
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Table 57 Address 00000
- CC Memory Map Word:bits W15:31:10 W15:9:8 Description X Transmit Fragmentation Header 00 - Short sequence 01 - Short sequence with class(PPP) 10 - Long sequence (PPP) 11 - Long sequence with class (PPP) Tx Fragmentation Mode 00 - Add Fragment Header 01 - Reserved 10 - Non sequenced 11 - Unused Fragmentation size 00 - 128 01 - 256 10 - 512 11 - packet Tx Sub-channel number Defines the offset/index of a member channel within a multilink group that is to be selected. Initial Sequence Number. X Transmit Multilink override 0 - No override 1 - Multilink override. The sub channel number is used to select from the multilink bundle. Tx Class of Service. Used only for PPP/ML_PPP. These bits must be set to 0 for correct operation.
Record Tx Unused TX_HDR_SZ[1:0]
TX_FRAG_MODE[1:0]
W15:7:6
TX_FRAG_SIZE[1:0]
Cin*16words
W15:5:4
(16x16K)
TX_SUB_CH_NUM[3:0]
W15:3:0
TX_SEQ_NUM[23:0] Unused TX_ML_OVRD
W14:31:8 W14:7 W14:6
TX_COS[3:0] TX Reserved
W14:5:2 W14:1:0
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Address Con't
Record Unused Unused Unused Unused Unused Unused Unused Rx Reserved Rx Reserved Rx Reserved Rx Reserved FIFO_ACT Rx Reserved Rx Reserved Rx Reserved RESEQ_ACT Rx Reserved Rx Reserved
Word:bits W13:31:0 W12:31:0 W11:31:0 W10:31:0 W9:31:0 W8:31:0 W7:31:0 W6:31:0 W5:31:0 W4:31:0 W3:31:13 W3:12 W3:11:0 W2:31:0 W1:31:16 W1:15 W1:14:0 W0:31:5 W0:4:1
Description X X X X X X X These bits must be set to 0 for correct operation. These bits must be set to 0 for correct operation. These bits must be set to 0 for correct operation. These bits must be set to 0 for correct operation. FIFO Active. 1 - Active 0 - Inactive These bits must be set to 0 for correct operation. These bits must be set to 0 for correct operation. These bits must be set to 0 for correct operation. Resequencing Active. 1 - Active 0 - Inactive These bits must be set to 0 for correct operation. These bits must be set to 0 for correct operation. Lost Timeout Period 0000 - Lost Detection off 1111-0001 - Timeout period in increments of 10ms (10ms - 150ms) Receive Class 0 - High Priority 1 - Low Priority Note: When writing W0, W1-W3 must also be written to 0.
Cin*16words
(16x16K =256K)
3FFFF LOST_CNT
RX_CLASS
W0:0
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12 TEST FEATURES DESCRIPTION The FREEDM-336A1024 also supports a standard IEEE 1149.1 five signal JTAG boundary scan test port for use in board testing. All device inputs may be read and all device outputs may be forced via the JTAG test port. 12.1 Test Mode Registers Test mode registers are used to apply test vectors to the DLL during production testing of the FREEDM-336A1024. Production testing is enabled by asserting the PMCTEST pin. During production tests, FREEDM-336A1024 registers are selected by the TA[12:0] pins. Read accesses are enabled by asserting TRDB low while write accesses are enabled by asserting TWRB low. Test mode register data is conveyed on the TDAT[15:0] pins. Test mode registers (as opposed to normal mode registers) are selected when TA[12]/TRS is set high.
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Table 58
- Test Mode Register Memory Map Register Normal Mode Registers Reserved DLL Test Registers Reserved
Address TA[12:0] 0x0000 - 0x0EFF 0x0F00 - 0x0F1F 0x1F20 - 0x1F2C 0x1F2D - 0x1FFF
Notes on Test Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. Writable test mode register bits are not initialized upon reset unless otherwise noted. 12.2 JTAG Test Port The FREEDM-336A1024 JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section. Table 59 - Instruction Register
Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Instruction Code IR[2:0] 000 001 010 011 100 101
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Instructions BYPASS BYPASS
Selected Register Bypass Bypass
Instruction Code IR[2:0] 110 111
12.2.1 Identification Register Length - 32 bits Version number - 1H Part Number - 7388H Manufacturer's identification code - 0CDH Device identification - 173880CDH
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13 OPERATIONS This section presents operating details for the JTAG boundary scan feature. 13.1 JTAG Support The FREEDM-336A1024 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below. Figure 32 - Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decodes, and a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers.
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The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a single bit delay from primary input, TDI to primary output , TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register placed in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs. TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
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Figure 33
- TAP Controller Finite State Machine
TRSTB=0
Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 0 1 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle The run test/idle state is used to execute tests.
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Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-IR The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
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Boundary Scan Instructions The following is a description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO. BYPASS The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out output, TDO using the Shift-DR state.
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INTEST The internal test instruction is used to exercise the device's internal core logic. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Update-DR state, patterns shifted in on input, TDI are used to drive primary inputs. During the Capture-DR state, primary outputs are sampled and loaded into the boundary scan register.
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14 FUNCTIONAL TIMING 14.1 SBI DROP BUS Interface Timing Figure 34
REFCLK C1FP DDATA[7:0] DPL DV5 DDP C1
- T1/E1 DROP BUS Functional Timing
*** *** *** *** *** *** V3 V3 V3 DS0#4. V5 DS0#9.
Figure 34 illustrates the operation of the SBI DROP BUS, using a negative justification on the second to last V3 octet as an example. The justification is indicated by asserting DPL high during the V3 octet. The timing diagram also shows the location of one of the tributaries by asserting DV5 high during the V5 octet. Figure 35
REFCLK C1FP DDATA[7:0] DPL DV5 DDP C1
- DS3 DROP BUS Functional Timing
*** *** *** *** *** *** H3 H3 H3 H3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #4
Figure 35 shows twelve DS3 tributaries mapped onto the SBI bus. A negative justification is shown for DS3 #11 during the H3 octet with DPL asserted high. A positive justification is shown for DS3#1 during the first DS3#1 octet after H3 which has DPL asserted low.
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14.2 SBI ADD BUS Interface Timing Figure 36
REFCLK C1FP ADATA[7:0] APL AV5 ADP AJUST_REQ C1
- DS3 Add Bus Adjustment Request Functional Timing
*** *** *** *** *** *** *** H3 H3 H3 H3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #4
Figure 36 illustrates the operation of the SBI ADD BUS, using positive and negative justification requests as an example. (The responses to the justification requests would take effect during the next multi-frame.) The negative justification request occurs on the DS3#12 tributary when AJUST_REQ is asserted high during the H3 octet. The positive justification occurs on the DS3#2 tributary when AJUST_REQ is asserted high during the first DS3#2 octet after the H3 octet. 14.3 Receive Link Timing The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals is shown in Figure 37. The receive data is viewed as a contiguous serial stream. There is no concept of time-slots or framing. Every eight bits are grouped together into a byte with arbitrary alignment. The first bit received (B1 in Figure 37) is deemed the most significant bit of an octet. The last bit received (B8) is deemed the least significant bit. Bits that are to be processed by the FREEDM336A1024 are clocked in on the rising edge of RCLK[n]. Bits that should be ignored (X in Figure 37) are squelched by holding RCLK[n] quiescent. In Figure 37, the quiescent period is shown to be a low level on RCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also acceptable. Selection of bits for processing is arbitrary and is not subject to any byte alignment or frame boundary considerations.
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
Figure 37
- Receive Link Timing
RCLK[n] RD[n]
B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X
14.4 Transmit Link Timing The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals is shown in Figure 38. The transmit data is viewed as a contiguous serial stream. There is no concept of time-slots or framing. Every eight bits are grouped together into a byte with arbitrary byte alignment. Octet data is transmitted from most significant bit (B1 in Figure 38) and ending with the least significant bit (B8 in Figure 38). Bits are updated on the falling edge of TCLK[n]. A transmit link may be stalled by holding the corresponding TCLK[n] quiescent. In Figure 38, bits B5 and B2 are shown to be stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure 38, the quiescent period is shown to be a low level on TCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also acceptable. Gapping of TCLK[n] can occur arbitrarily without regard to byte or frame boundaries. Figure 38 - Transmit Link Timing
TCLK[n] TD[n]
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2
14.5 Receive APPI Timing (ANY-PHY Level 2) The receive ANY-PHY packet interface (APPI) timing is shown in Figure 39 through Figure 42 when the ANY-PHY interface operates at 52 MHz, 16 bits of RXDATA are valid. The FREEDM-336A1024 device provides data to an external controller using the receive APPI. The following discussion surrounding the receive APPI functional timing assumes that multiple FREEDM-336A1024 devices share a single external controller. All Rx APPI signals are shared between the FREEDM-336A1024 devices
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
Figure 39
RXCLK RXADDR[3:0] RPA RENB XDATA[15:0] RVAL RSX REOP RMOD RERR RSOP Dev 0 NULL Dev 7 Dev 0
- Receive APPI Timing (Normal Transfer 16 bit 52 MHz)
NULL
Dev 6 Dev 7
NULL
Dev 4 Dev 6
NULL
Dev 0 Dev 4
NULL
Dev 1 Dev 0
NULL
Dev 3 Dev 1
NULL
Dev 2 Dev 3
NULL Dev 2
CH 2
D0
Dev 0 D1
Dev 0 D2 D3 D4 D5 D6 D7
Figure 39 shows the transfer of an 8 word packet across the Rx APPI from FREEDM-336A1024 device 0, ANY-PHY channel 2. In this example, seven FREEDM-336A1024 devices are sharing the Rx APPI, with device 5 being the null address. The data transfer begins when the external controller selects FREEDM336A1024 device 0 by placing that address on the RXADDR[3:0] inputs and setting RENB high. The external controller sets RENB low in the next RXCLK cycle to commence data transfer across the Rx APPI. The FREEDM-336A1024 samples RENB low and responds by asserting RSX one RXCLK cycle later. The start of all burst data transfers is qualified with RSX and an in-band ANY-PHY channel address on RXDATA[15:0] to associate the data to follow with an ANYPHY channel. During the cycle when D2 is placed on RXDATA[15:0], the external controller is unable to accept any further data and sets RENB high. Two RXCLK cycles later, the FREEDM-336A1024 tristates the Rx APPI. The external controller may hold RENB high for an indeterminate number of RXCLK cycles. The FREEDM336A1024 will wait until the external controller returns RENB low. Because the FREEDM-336A1024 does not support interrupted data transfers on the Rx APPI, the external controller must reselect FREEDM-336A1024 device 0 or output a null address during the clock cycle before it returns RENB low. However, while RENB remains high, the address on the RXADDR[3:0] signals may change. When the FREEDM-336A1024 device 0 samples RENB low, it continues data transfer by providing D4 on RXDATA[15:0]. Note that if D3 were the final word of the packet (Status), in response to sampling REOP high, the external controller does not have to reselect FREEDM-336A1024 device 0. This is shown in Figure 42. The FREEDM-336A1024 will not pause burst data transfers across the Rx APPI.
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
The FREEDM-336A1024 automatically deselects at the end of all burst data transfers. The FREEDM-336A1024 must be reselected before any further data will be transferred across the Rx APPI. The RVAL and REOP signals indicate the presence and end of valid packet data respectively. The RERR and RMOD signals are only valid at the end of a packet and are qualified with the REOP signal. When a packet is erred, the FREEDM336A1024 may be programmed to overwrite RXDATA[15:0] in the final word of packet transfer with status information indicating the cause of the error. RXDATA[15:0] is not modified if a packet is error free. The RXADDR[3:0] signals serve to poll FREEDM-336A1024 devices as well as for selection. During data transfer, the RXADDR[3:0] signals continue to poll the FREEDM-336A1024 devices sharing the Rx APPI. Polled results are returned on the RPA signal. Note that each poll address is separated by a NULL address to generate tristate turn-around cycle in order to prevent multiple FREEDM336A1024 devices from briefly driving RPA. If RPA is a point-to-point signal for each FREEDM-336A1024 device on the board, then the tristate turn-around cycle is not required, thereby effectively doubling the polling bandwidth at the expense of extra signals. Polled results reflect the status of the Rx APPI. Polled responses always refer to the next segment transfer. In other words, polled responses during or after the RXCLK cycle where RSX is set high refer to a segment that is not involved in the current data transfer. This allows the external controller to gather knowledge about the segment not involved in the current segment transfer so that it can anticipate reselecting that FREEDM-336A1024 device (via RENB) to maximize bandwidth on the Rx APPI (shown in Figure 41). Figure 40
RXCLK RXADDR[3:0] RPA RENB RXDATA[15:0] RVAL RSX REOP RMOD RERR RSOP CH 2 D0 Dev 0 D1 D98 D99 CH 8 Dev 0 D0 D1 Dev 0 NULL Dev 7 Dev 0 NULL Dev 6 Dev 7 NULL Dev 4 NULL Dev 4 Dev 0 NULL Dev 0 Dev 3 NULL Dev 2 Dev 3 NULL Dev 2
- Receive APPI Timing (Auto Deselection)
Figure 40 shows the transfer of a 100 word packet across the Rx APPI from FREEDM-336A1024 device 0, channel 2 followed by the transfer of a 2 word
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
packet from FREEDM-336A1024 device 0, channel 8. More importantly, Figure 40 illustrates that, for back-to-back transfers from the same FREEDM-336A1024 (device 0), it must be reselected before any further data is provided on the Rx APPI. At the end of the first 100 word packet transfer across the Rx APPI, the FREEDM-336A1024 automatically deselects and must be reselected before the second two word packet is transferred. When the external controller samples REOP high, it recognizes that the burst transfer has completed. Two RXCLK cycles later, the external controller reselects FREEDM-336A1024 device 0 by setting RENB high and placing address 0 on the RXADDR[3:0] signals. When the FREEDM-336A1024 samples RENB low, it begins the next data transfer as before. Figure 41
RXCLK RXADDR[3:0] RPA RENB Dev 0 RXDATA[15:0] RVAL RSX REOP RMOD RERR RSOP CH 2 D0 D1 D125 D126 D127 CH 2 Dev 0 D128 Dev 0 NULL Dev 7 Dev 0 NULL Dev 6 Dev 7 NULL NULL Dev 0 NULL Dev 4 Dev 0 NULL Dev 4 Dev 3 NULL
- Receive APPI Timing (Optimal Reselection)
Figure 41 shows optimal bandwidth utilization across the Rx APPI. With knowledge that the maximum burst data transfer (excluding ANY-PHY channel address prepend) is 256 bytes, i.e. 128 words, the external controller th sets RENB high when the 127 word (D126) is placed on RXDATA[15:0] in anticipation of the end of a burst transfer. The FREEDM-336A1024 completes the burst data transfer and tristates the Rx APPI one RXCLK cycle after RENB is sampled high. Because the burst data transfer is complete and RENB is immediately returned low following selection, the FREEDM-336A1024 immediately begins the next data transfer following the single turn-around cycle. The protocol dictates that at least one tristate turn-around cycle be inserted between data transfers, even if the external controller is reselecting the same FREEDM-336A1024 device. In other words, Figure 41 shows the earliest possible time that the external controller could have set RENB high to reselect FREEDM-336A1024 device 0.
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Figure 42
RXCLK RXADDR[3:0] RPA RENB RXDATA[15:0] RVAL RSX REOP RMOD RERR RSOP Dev 0 NULL
- Receive APPI Timing (Boundary Condition)
Dev 7 Dev 0
NULL
Dev 6 Dev 7
NULL
Dev 4 Dev 6
NULL Dev 4
Dev 7
Dev 1
NULL Dev 7
Dev 3 Dev 1
NULL
Dev 2 Dev 3
NULL Dev 2
CH 2
D0
D1
D2
D3
CH 1
Dev 7 D8
D9
Figure 42 shows the boundary condition where a packet transfer completes shortly after the external controller has set RENB high to pause the FREEDM336A1024 device. The second data transfer is the final two words of a packet for FREEDM-336A1024 device 7, channel 1. When FREEDM-336A1024 device 0 places D2 on RXDATA[15:0], the external controller sets RENB high to pause the FREEDM-336A1024 device. In the following RXCLK cycle, the FREEDM-336A1024 provides D3 on RXDATA[15:0] and sets REOP high to conclude packet transfer. The external controller samples REOP high while RENB is high and recognizes that the packet transfer is complete. The external controller now knows that it doesn't need to reselect FREEDM-336A1024 device 0, but can select another FREEDM-336A1024 device sharing the Rx APPI. The external controller decides to select FREEDM336A1024 device 7 by placing this address on the RXADDR[3:0] signals. The external controller sets RENB low to commence data transfer from FREEDM336A1024 device 7. 14.6 Transmit APPI Timing (ANY-PHY Level 2) The transmit ANY-PHY packet interface (APPI) timing is shown in Figure 43. An external controller provides data to the FREEDM-336A1024 device using the transmit APPI. The following discussion surrounding the transmit APPI functional timing assumes that multiple FREEDM-336A1024 devices share a single external controller. The FREEDM-336A1024 compares the TXADDR[15:0] to the base and range address registers to determine if the poll request is destined for the particular FREEDM-336A1024. All Tx APPI signals are shared between the FREEDM-336A1024 devices.
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Figure 43
TXCLK TRDY TXDATA[15:0] TSX TEOP TMOD TERR CH 0
- Transmit APPI Timing (Normal Transfer)
D0
D1
D2
D126 D127 CH 0 D128 D129
D130
D131 D132 D254 D255
Figure 43 shows transfer of a 256 word packet on the Tx APPI for ANY-PHY channel 0. The maximum burst data transfer (excluding channel address prepend) is 128 words, so two data transfers are required to complete the transfer of the 256 word packet. The start of all burst data transfers is qualified with the TSX signal and an in-band channel address on TXDATA[15:0] to associate the data to follow with an ANY-PHY channel. The TEOP signal indicates the end of valid packet data. The TMOD and TERR signals are held low except at the end of a packet (TEOP set high). The FREEDM-336A1024 starts driving the TRDY signal one TXCLK cycle after TSX is sampled high. Upon sampling the TRDY signal high, the external controller completes the current burst data transfer. The FREEDM-336A1024 tristates the TRDY signal one TXCLK cycle after it has been driven high. This is the case for the first burst data transfer in Figure 43. In the second burst data transfer, the FREEDM-336A1024 drives the TRDY signal low to indicate that the FIFO in the Tx APPI is full and no further data may be transferred. Upon sampling the TRDY signal low, the external controller must hold the last valid word of data on TXDATA[15:0]. The FREEDM-336A1024 may drive TRDY low for an indeterminate number of TXCLK cycles. During this time, the external controller must wait and is not permitted to begin another burst data transfer until TRDY is sampled high. When there is space in the Tx APPI FIFO, the FREEDM336A1024 drives the TRDY signal high. Upon sampling the TRDY signal high, the external controller completes the current burst data transfer. The FREEDM336A1024 tristates the TRDY signal one TXCLK cycle after it has been driven high. The external controller must sample the TRDY signal high and must then wait one clock cycle before it can begin the next burst data transfer. This prevents the external controller from bombarding the FREEDM-336A1024 device with small packets and allows the FREEDM-336A1024 to perform the necessary housekeeping and clean up associated with the ending of burst data transfers. In addition, the rule that TSX must be a minimum of 4 clock cycles apart must be adhered to. This protocol also ensures that transitions between burst data
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
transfers do not require any extra per ANY-PHY channel storage, thereby simplifying implementation of both the external controller and the FREEDM336A1024 device. Figure 44 illustrates this condition. Alternatively, the external controller can enforce a minimum separation between packets ensuring that FREEDM-336A1024 will have enough time to perform the necessary housekeeping and clean up. In this situation, the external controller does not need to sample TRDY. Figure 44
TXCLK TRDY TXDATA[15:0] TSX TEOP TMOD TERR CH 0 D0 CH 3 D0 D1 D2 CH 2 D0
- Transmit APPI Timing (Special Conditions)
Figure 44 shows two special conditions - (1) the transfer of a one word packet, illustrating how the external controller must wait until TRDY has been sampled high before the next data transfer can begin, and (2) the transfer of a packet that completes when TRDY is set low, illustrating that although the packet has been completely transferred, the external controller must still wait until TRDY has been sampled high before the next data transfer can begin. The first data transfer is a single word packet for ANY-PHY channel 0. The FREEDM-336A1024 asserts TRDY high one TXCLK cycle after TSX is sampled high. The Tx APPI protocol dictates that the external controller must wait until one clock after TRDY is sampled high before beginning the next data transfer for ANY-PHY channel 3. The external controller must hold the last valid word on TXDATA[15:0] until TRDY is sampled high. In this case, that data is a don't care. The FREEDM-336A1024 tristates the TRDY signal one TXCLK cycle after it has been driven high. The second transfer is a three word packet, which completes transfer in the same TXCLK cycle that TRDY is sampled low by the external controller. Again, the external controller must hold the last valid word on TXDATA[15:0] until TRDY is sampled high. In this case, that data is D2, the last word of the packet. The FREEDM-336A1024 may drive TRDY low for an indeterminate number of TXCLK cycles. During this time, the external controller must wait and is not permitted to begin another burst data transfer until TRDY is sampled high. When the external controller samples TRDY high, the current burst transfer is deemed to be complete and the external controller may begin the next data transfer. The FREEDM-336A1024 tristates the TRDY signal one TXCLK cycle after it has been driven high.
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
Figure 45
- Transmit APPI Poll Timing
TXCLK TXADDR[15:0] TPA CH 1023 CH 0 CH 254 CH 1023 CH 8 CH 0 NULL CH 254 CH 8 CH 0 CH 399 NULL NULL1 CH 399
CH 0
When supporting ANY-PHY Level 2, polling is completely decoupled from device and ANY-PHY channel selection on the Tx APPI (Figure 45). Accordingly, the TXADDR[15:0] signals continue to provide only a poll address for any of the FREEDM-336A1024 devices sharing the Tx APPI. The FREEDM-336A1024 compares the TXADDR[15:0] to the base and range address registers to determine if the channel being polled resides within the device. Poll results are returned on the TPA signals. The TPA bit indicates whether or not space to accept 9600 bytes in packet mode exists in the ANY-PHY channel FIFO for data (high means space exists in the ANY-PHY channel FIFO). 14.7 Receive APPI Timing (ANY-PHY Level 3) The receive ANY-PHY packet interface (APPI) timing is shown in Figure 46 when the ANY-PHY interface operates at 104 MHz, RXDATA[7:0] are valid. The FREEDM-336A1024 device provides data to an external controller using the receive APPI. Figure 46
RXCLK RENB RXDATA[7:0] RVAL RSX RSOP REOP RERR RXPRTY CH 2 CH 2 D1 D2 D3 D4 D5 D6 D7
- Receive APPI Timing (Normal Transfer 8 bit 104 MHz)
Figure 46 shows the transfer of an 8 byte packet across the Rx APPI from FREEDM-336A1024. The external controller sets RENB low to commence data transfer across the Rx APPI. The FREEDM-336A1024 samples RENB low and responds by asserting RSX one RXCLK cycle later. The start of all burst data transfers is qualified with RSX and an in-band ANY-PHY channel address on RXDATA[7:0] to associate the data to follow with an ANY-PHY channel. The RSOP signal is asserted 2 cycles after the RSX allowing the controller to identify
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
the start of packet. The first two bytes indicate the ANY-PHY channel (CH 2) while the next two bytes contain either a connection identifier or the first two bytes of the packet. During the cycle when D2 is placed on RXDATA[7:0], the external controller is unable to accept any further data and sets RENB high. Two RXCLK cycles later, the FREEDM-336A1024 pauses the Rx APPI. The external controller may hold RENB high for an indeterminate number of RXCLK cycles. The FREEDM336A1024 will wait until the external controller returns RENB low. The FREEDM-336A1024 will not pause burst data transfers across the Rx APPI. The RVAL and REOP signals indicate the presence and end of valid packet data respectively. The RERR and RMOD signals are only valid at the end of a packet and are qualified with the REOP signal. When a packet is erred, the FREEDM336A1024 may be programmed to overwrite RXDATA[7:0] in the final word of packet transfer with status information indicating the cause of the error. RXDATA[7:0] is not modified if a packet is error free 14.8 Transmit APPI Timing (ANY-PHY Level 3) The transmit ANY-PHY packet interface (APPI) timing is shown in Figure 47 through Figure 49. An external controller provides data to the FREEDM336A1024 device using the transmit APPI. The following discussion surrounding the transmit APPI functional timing assumes that point to point interfaces exist between FREEDM-336A1024 and the external controller. The FREEDM336A1024 compares the TXADDR[15:0] to the base and range address registers to determine if the address is destined for the FREEDM-336A1024. Figure 47
TXCLK TRDY TXDATA[7:0] TSX TEOP TERR TXPRTY CH 0 CH 0 CI 1 CI 2 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D252 D253
- Transmit APPI Timing ANY-PHY Level 3 (Normal Transfer)
Figure 47 shows transfer of a 254 byte packet on the Tx APPI of FREEDM336A1024. The start of all burst data transfers is qualified with the TSX signal and an in-band ANY-PHY channel address on TXDATA[7:0] to associate the data
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
to follow with an ANY-PHY channel. The TEOP signal indicates the end of valid packet data. The TERR signal is held low except at the end of a packet (TEOP set high). The TRDY signal is valid one TXCLK cycle after TSX is sampled high. Upon sampling the TRDY signal high, the external controller completes the current burst data transfer. This is the case for the first burst data transfer in Figure 47. In Figure 48, the FREEDM-336A1024 drives the TRDY signal low to indicate that the FIFO in the Tx APPI are full and no further data may be transferred. Upon sampling the TRDY signal low, the external controller must hold the last valid word of data on TXDATA[7:0]. The FREEDM-336A1024 may drive TRDY low for an indeterminate number of TXCLK cycles. During this time, the external controller must wait and is not permitted to begin another burst data transfer until TRDY is sampled high. Upon sampling the TRDY signal high, the external controller completes the current burst data transfer. The external controller can sample the TRDY signal high before it can begin the next burst data transfer. TRDY is provided to prevent the external controller from bombarding the FREEDM-336A1024 device with small packets and allows the FREEDM-336A1024 to perform the necessary housekeeping and clean up associated with the ending of burst data transfers. In addition, the rule that TSX must be a minimum of 4 clock cycles apart must be adhered. This protocol also ensures that transitions between burst data transfers do not require any extra per ANY-PHY channel storage, thereby simplifying implementation of both the external controller and the FREEDM-336A1024 device. Figure 48 illustrates this condition. Alternatively, the external controller can enforce a minimum separation between packets ensuring that FREEDM-336A1024 will have enough time to perform the necessary housekeeping and clean up. In this situation, the external controller does not need to sample TRDY. Figure 48
TXCLK TRDY TXDATA[7:0] TSX TEOP TERR CH 3 CH3 D0 D1 CH2 CH2 D0 D1
- Transmit APPI Timing ANY-PHY Level 3 (Special Condition)
Figure 48 shows a special condition where the transfer of a packet that completes when TRDY is set low, illustrating that although the packet has been completely transferred, the external controller must still wait until TRDY has been sampled high before the next data transfer can begin.
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
The illustrated transfer is a two byte packet, which completes transfer in the same TXCLK cycle that TRDY is sampled low by the external controller. The external controller must hold the last valid byte on TXDATA[7:0] until TRDY is valid and sampled high. In this case, that data is D1, the last byte of the packet. The FREEDM-336A1024 may drive TRDY low for an indeterminate number of TXCLK cycles. During this time, the external controller must wait and is not permitted to begin another burst data transfer until TRDY is valid and sampled high. When the external controller samples TRDY high, the current burst transfer is deemed to be complete and the external controller may begin the next data transfer. Figure 49 - Transmit APPI Polling Timing (ANY-PHY Level 3)
TXCLK TXADDR[15:0] TPA CH 1023 CH 0 CH 254 CH 1023 CH 8 CH 0 NULL CH 254 CH 8 CH 0 CH 399 NULL NULL1 CH 399
CH 0
When supporting ANY-PHY Level 3 mode polling is completely decoupled from data transfer on the Tx APPI (Figure 49) with the restriction that the TPA poll result is invalid for all channels if it corresponds to a TXADDR poll coincident with the start of transfer (ie the cycle in which TSX is driven high). Accordingly, the TXADDR[15:0] signals continue to provide only a poll address for the FREEDM336A1024 device The FREEDM-336A1024 compares the TXADDR[15:0] to the base and range address registers to determine if the ANY-PHY channel being polled resides within the device. Poll results are returned on the TPA signal. The TPA bit indicates whether or not space exists in the ANY-PHY channel FIFO for a 9600 byte packet (high means space exists in the ANY-PHY channel FIFO). For unprovisioned channels, TPA=0. 14.9 Re-Sequencing SDRAM Interface The following two diagrams depict the timing for signals destined for the pins of the Re-sequencing SDRAM during the Activate-Read (with Auto-precharge), and Activate-Write (with Auto-precharge sequences.
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
Figure 50
- Read Timing for Re-Sequencing memory
SYSCLK RSCSB RSRASB RSCASB RSWEB RSADD[12:0] RSBS[1:0] RSADD[10] RSDAT[31:0]
ROW ADDR BANK ADDR ROW ADDR COL ADDR0 COL_ADDR1 COL_ADDR2 BANK ADDR BANK ADDR BANK ADDR Dis Auto Prech Dis. Auto PrechEn. Auto Prech RD_W0 RD_W1 RD_W2
Figure 51
- Write Timing Re-Sequencing memory
SYSCLK RSCSB RSRASB RSCASB RSWEB RSADD[12:0] RSBS[1:0] RSADD[10] RSDAT[47:0]
ROW ADDR BANK ADDR ROW ADDR COL ADDR BANK ADDR Dis Auto Pre WR_W0 COL ADDR BANK ADDR Dis Auto Pre WR_W1 COL ADDR BANK ADDR En Auto Pre WR_W2
14.10 Chunk Buffer SDRAM Interface The following two diagrams depict the timing for signals destined for the pins of the Chunk Buffer SDRAM during the Activate-Read (with Auto-precharge), and Activate-Write (with Auto-precharge sequences. )
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
Figure 52
- Read Timing for Chunk Buffer memory
SYSCLK CBCSB CBRASB CBCASB CBWEB CBADD[12:0] CBBS[1:0] CBADD[10] CBDAT[47:0]
ROW ADDR BANK ADDR ROW ADDR COL ADDR BANK ADDR EN/DIS Auto Pre RD_W0 RD_W1 RD_W2 RD_Wn
Figure 53
- Write Timing for Chunk Buffer memory
SYSCLK CBCSB CBRASB CBCASB CBWEB CBADD[12:0] CBBS[1:0] CBADD[10] CBDAT[47:0]
ROW ADDR BANK ADDR ROW ADDR COL ADDR BANK ADDR En/Dis Auto Pre WR_W0 WR_W1 WR_W2 WR_Wn
14.11 Context SSRAM Interface (ZBT SSRAM mode) The following diagrams depict the timing for the pipelined ZBT SSRAM and Standard SSRAM during a read followed by a write cycle. Figure 54
1 SYSCLK CC_ADDR[17:0] CC_WEB CC_SELB CC_RDDATA [35:0] CC_WRDATA[35:0]
Q0 Q1 D0 D1 Q2 R0 R1 W0 W1 R2
- Read followed by Write Timing for ZBT mode
2 3 4 5 6 7 8 9
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FRAME ENGINE AND DATA LINK MANAGER 336A1024
Figure 55
1 SYSCLK CC_ADDR[17:0] CC_WEB CC_SELB CC_RDDATA [35:0] CC_WRDATA[35:0]
R0 R1
- Read followed by Write Timing for Standard SSRAM mode
2 3 4 5 6 7 8 9 10
W0
W1
R2
Q0
Q1 D0 D1
Q2
14.12 Microprocessor Interface The following diagrams illustrate the various handshaking required for microprocessor reads and writes. Figure 56 shows a single read and write operation to the non-burstable register space with bus polarity set to 1. On the first cycle, BURSTB is sampled inactive; therefore, it is expected that the cycle is a single data transfer, and the BLAST signal is of no significance. The subsequent 2 cycles have BURSTB sampled active hence the transfer cycle is terminated when both BLAST and READYB are asserted. Note that between each transfer, there is a turn around cycle provided by the external interface to ensure that there is no bus contention on back to back transfers on the AD bus. Figure 56
1 BCLK BUSPOL CSB ADSB AD(31:0) WR BURSTB BLAST READYB BTERMB A D A D A D 2
- Read and Write to non-burstable register space
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Read, 3 wait cycles
Write, 1 wait cycle
Read, 4 wait cycles
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Figure 57 shows a burst read and write operation (only valid for burstable registers) with bus polarity set to 0. The first and third accesses illustrate transfers that are terminated by the FREEDM-336A1024 via the assertion of BTERMB. The second and fourth accesses illustrate transfers that are terminated by the external interface via the assertion of BLAST. Note that between each transfer, there is no turn around cycle. Care must be taken to examine the AC timing to ensure that there is no bus contention on the AD bus between a read followed by a write transfer. BTERMB is only asserted when the burst access is 4 cycles long. It is not asserted if the burst cycle is terminated by BLAST or for non-burst accesses (BURSTB=1). Figure 57 Read and Write to burstable address space
1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233343536 Burst read, 3 wait cycles, mbtermb used Burst read, 4 wait cycles, no mbtermb Burst write, 1 wait cycle, mbterm Burst read, 3 BCLK BUSPOL CSB ADSB AD(31:0) WR BURSTB BLAST READYB BTERMB
A D A D A D A D D A D
Figure 58 shows consecutive write operations using the WRDONEB signal without the READYB. Write operations may only begin when WRDONEB is sampled low by the external interface. On the first data transfer, the cycle is terminated normally. Subsequent access does not begin until WRDONEB is sampled low by the external interface. This interface is used when the external processor is incapable of dealing with wait states during write
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Figure 58
1 BCLK BUSPOL CSB AD[31:0] WR BURSTB BLAST WRDONEB 2
- Consecutive Write Accesses Using WRDONEB
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
A
D0
A
D0
D1
D2
D2
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15 ABSOLUTE MAXIMUM RATINGS Maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal operating conditions. Table 60 - FREEDM-336A1024 Absolute Maximum Ratings -40C to +85C -40C to +125C -0.3V to +4.6V -0.3V to +2.98 V -0.3V to VDD3.3 + 0.3V 1000 V 100 mA 20 mA +230C +120 C
Ambient Temperature under Bias Storage Temperature Supply Voltage (+3.3 Volt VDD3.3) Supply Voltage (+1.8 Volt VDD1.8) Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature
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16 D.C. CHARACTERISTICS (TA = -40C to +85C, VDD3.3 = 3.0 to 3.6 V, VDD1.8 = 1.71 to 1.94 V ) Table 61 Symbol VDD3.3 VDD1.8 VIL VIH VOL - FREEDM-336A1024 D.C. Characteristics Min 3.0 1.71 -0.3 2.0 Typ 3.3 1.8 Max 3.6 1.94 0.8 Units Volts Volts Volts Note 5. Note 5. Conditions
Parameter 3.3V Power Supply 1.8V Power Supply Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage
VDD3.3 Volts + 0.3 0.4 Volts IOL = -9 mA for all outputs except TDO where IOL = -6 mA, and AD[31:0], READYB, BTERMB, WRDONEB where IOL = 12 mA. Note 3. IOH = 9 mA for all outputs except TDO where IOH = 6 mA, and AD[31:0], READYB, BTERMB, WRDONEB where IOH = 12 mA. Note 3. VIL = GND, Notes 1, 3, 5. VIH = VDD, Notes 1, 3 VIL = GND, Notes 2, 3 VIH = VDD, Notes 2, 3 Excludes package. Package typically 2 pF. Note 5.
VOH
Output or Bidirectional High Voltage
2.4
Volts
IILPU IIHPU IIL IIH CIN
Input Low Current Input High Current Input Low Current Input High Current Input Capacitance
+10 -10 -10 -10
45 0 0 0 5
+100 +10 +10 +10
A A A A pF
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Symbol COUT
Parameter Output Capacitance Bi-directional Capacitance Pin Inductance
Min
Typ 5
Max
Units pF
Conditions All pins. Excludes package. Package typically 2 pF. Note 5. All pins. Excludes package. Package typically 2 pF. Note 5. All pins. Note 5. VDD1.8 = 1.8V, Outputs Unloaded. All 12 SPEs on SBI interface active VDD3.3= 3.3V, Outputs reasonably loaded. All 12 SPEs on SBI interface active.
CIO
5
pF
LPIN
2
nH A
IDDOP1V8 Operating Current, core
IDDOP3V3 Operating Current, I/O Ring
A
Notes on D.C. Characteristics: 1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up resistor. 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. Input pin or bi-directional pin with internal pull-down resistor. 5. Typical values are given as a design aid. The product is not tested to the typical values given in the data sheet.
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17 FREEDM-336A1024 TIMING CHARACTERISTICS (TA = -40C to +85C, VDD3.3 = 3.0 to 3.6 V, VDD1.8 = 1.71 to 1.94 V ) Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
2.
Notes on Output Timing: 1. 2. 3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. Loads used to measure maximum output propagation delays are specified with each table. 0pF load is used to measure minimum output propagation delays.
Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current transfer. 17.1 SBI Bus Interface Timing Table 62 Symbol fCLK DCLK - REFCLK Timing Description Frequency, REFCLK =77.76MHz Duty Cycle, REFCLK Min -20 40 Max +20 60 Units ppm %
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Figure 59
- SBI336 Drop Bus Input Interface Timing
REFC LK tS C 1 F P D C 1FP tS D D P DDP tS D D A T A D D A T A [7 :0 ] tS D P L DPL tS D V 5 DV5 tH D V 5 tH D P L tH D D A T A tH D D P tH C 1 F P
Table 63 Symbol tSC1FP tHC1FP tSDDATA tHDDATA tSDPL tHDPL tSDV5 tHDV5 tSDDP tHDDP
- SBI336 Drop Bus Input Timing (referenced to (Figure 59)) Parameter REFCLK to Valid DC1FP Set-up Time REFCLK to Valid DC1FP Hold Time REFCLK to Valid DDATA Set-up Time REFCLK to Valid DDATA Hold Time REFCLK to Valid DPL Set-up Time REFCLK to Valid DPL Hold Time REFCLK to Valid DV5 Set-up Time REFCLK to Valid DV5 Hold Time REFCLK to Valid DDP Set-up Time REFCLK to Valid DDP Hold Time Min 2 0 2 0 2 0 2 0 2 0 Max Units ns ns ns ns ns ns ns ns ns ns
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17.2 SBI Add Bus Interface Timing Figure 60
REFCLK TSAC1FP AC1FP TSAJRQ AJUST_REQ tHAJRQ THAC1FP
- SBI336 Add Bus Input Interface Timing
Table 64 Symbol TSAC1FP THAC1FP TSAJRQ THAJRQ Notes:
- SBI336 Add Bus Input Timing (referenced to Figure 60 ) Parameter REFCLK to Valid AC1FP Set-up Time REFCLK to Valid AC1FP Hold Time REFCLK to Valid AJUST_REQ Set-up Time REFCLK to Valid AJUST_REQ Hold Time Min 2 0 2 0 Max Units ns ns ns ns
1. Input setup and hold times do not apply to ADETECT[1:0].
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Figure 61
REFCLK
- SBI336 Add Bus Output Interface Timing
tPAACT AACTIVE tPADATA tZADATA ADATA[7:0] tPAPL tZAPL APL tPAV5 tZAV5 AV5 tPADP tZADP ADP PC1FP C1FPOUT ZC1FP
Figure 62
- SBI ADD BUS Collision Avoidance Timing
ADETECT[n]
tP OUTEN ADATA[7:0], ADP, APL, AV5
tZ OUTEN
Table 65 - SBI336 Add Bus Output Timing (referenced to (Figure 61 and Figure 62)) Symbol tPAACT tPADATA tZADATA tPAPL Parameter REFCLK Edge to AACTIVE Prop Delay REFCLK Edge to ADATA Prop Delay REFCLK Edge to ADATA Output Tristate (see note 3) REFCLK Edge to APL Prop Delay Min 1 1 1 1 Max 8 8 9 8 Units ns ns ns ns
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Symbol tZAPL tPAV5 tZAV5 tPADP tZADP TPC1FP TPOUTEN
Parameter REFCLK Edge to APL Output Tristate (see note 3) REFCLK Edge to AV5 Prop Delay REFCLK Edge to AV5 Output Tristate (see note 3) REFCLK Edge to ADP Prop Delay REFCLK Edge to ADP Output Tristate (see note 3) REFCLK Edge to C1FPOUT Prop Delay ADETECT[1] and ADETECT[0] low to All SBI ADD BUS Outputs (except AACTIVE) Valid ADETECT[1] or ADETECT[0] high to All SBI ADD BUS Outputs (except AACTIVE) Tristate
Min 1 1 1 1 1 1 2
Max 9 8 9 8 9 9 10
Units ns ns ns ns ns ns ns
TZOUTEN
2
10
ns
Notes: 1. Although the AJUST_REQ is referenced to the Drop bus DC1FP alignment the timing from REFCLK is independent of the Add or Drop side of the SBI336 bus. 2. Maximum output propagation delays are measured with a 50pF load on the outputs except C1FPOUT, which is measured with a 100pF load. 3. This number is only relevant when the DEFAULT_DRV register bit in F336 SBI ADD BUS Master Configuration register is low indicating the bus is not always driven. 17.3 Serial Clock and Data Timing Table 66 Symbol - Clock/Data Input (Figure 37) Description RCLK[11:0] Frequency RCLK[11:0] Duty Cycle 40 Min Max 52 60 Units MHz %
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Symbol tSRD tHRD Figure 63
Description RD[11:0] Set-Up Time RD[11:0] Hold Time - Receive Data Timing
Min 2 1.5
Max
Units ns ns
RCLK[n] tS RD RD[n] tH RD
Table 67 Symbol
- Clock/Data Output (Figure 38) Description TCLK[11:0] Frequency TCLK[11:0] Duty Cycle 40 3 Min Max 52 60 12 Units MHz % ns
tPTD Notes:
TCLK[11:0] Low to TD[11:0] Valid
1. Maximum output propagation delays are measured with a 50pF load on the output. Figure 64 - Transmit Data Timing
TCLK[n] tP TD TD[n]
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17.4 ANY-PHY Timing Table 68 Symbol - ANY-PHY Level 2 Interface (Figure 65 and Figure 66) Description RXCLK Frequency RXCLK Duty Cycle TXCLK Frequency TXCLK Duty Cycle tSAPPI tHAPPI tPAPPI tZAPPI tZDAPPI All APPI Input Set-up time to RXCLK, TXCLK All APPI Input Hold time to RXCLK, TXCLK RXCLK, TXCLK to all APPI Outputs Valid RXCLK, TXCLK to APPI Outputs Tristate RXCLK, TXCLK to APPI Outputs Driven Min 25 40 25 40 4 0.6 1 1 0 12 12 Max 52 60 52 60 Units MHz % MHz % ns ns ns ns ns
Notes: 1. Maximum output propagation delays are measured with a 50pF load on the output.
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Table 69 Symbol
- ANY-PHY Level 3 Interface (Figure 65 and Figure 66) Description RXCLK Frequency RXCLK Duty Cycle TXCLK Frequency TXCLK Duty Cycle Min 52 40 52 40 2 0.6 1.5 6.5 Max 104 60 104 60 Units MHz % MHz % ns ns ns
tSAPPI tHAPPI tPAPPI Notes:
All APPI Input Set-up time to RXCLK, TXCLK All APPI Input Hold time to RXCLK, TXCLK RXCLK, TXCLK to all APPI Outputs Valid
1. Maximum output propagation delays are measured with a 20pF load on the output.
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Figure 65
- Receive ANY-PHY Interface Timing
RXCLK tSAPPI RXADDR[3:0] RENB RSOP RPA, RSX, RVAL RXDATA[15:0] RXPRTY, RERR REOP, RMOD RSOP RPA, RSX, RVAL RXDATA[15:0] RXPRTY, RERR REOP, RMOD RSOP RPA, RSX, RVAL RXDATA[15:0] RXPRTY, RERR REOP, RMOD tPAPPI tHAPPI
tZAPPI
tZDAPPI
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Figure 66
- Transmit ANY-PHY Interface Timing
TXCLK TXADDR[15:0] TXDATA[15:0] TXPRTY, TSX TEOP, TMOD TERR TPA TRDY tZAPPI TPA TRDY tZDAPPI TPA TRDY 17.5 Microprocessor Timing Table 70 Symbol fCLK DCLK Ts Th Tp Tz Tzb - Microprocessor Interface (Figure 67) Description Frequency, BCLK Duty Cycle, BCLK Input Set-up time to BCLK Input Hold time to BCLK BCLK High to Output Valid BCLK High to Output HighImpedance BCLK High to Output Driven Min 0 40 4.0 0.5 2.0 2.0 2.0 9.5 9.5 Max 66 60 Units MHz % ns ns ns ns ns tSAPPI tHAPPI
tPAPPI
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Notes: 1. Maximum output propagation delays are measured with a 50pF load on the output. 2. Input setup and hold times do not apply to BUSPOL. 3. Output Valid delays do not apply to INTHIB and INTLOB. 17.6 Memory Timing Figure 67 - Synchronous I/O Timing
CLK Ts Input Tp Tz Output Tzb Th
Table 71 Symbol fCLK DCLK
- SYSCLK Timing Description Frequency, SYSCLK Duty Cycle, SYSCLK Min 80 40 Max 100 60 Units MHz %
Table 72 Symbol Ts Th Tp Tz
- Resequencing SDRAM Interface (Figure 67) Description Input Set-up time to SYSCLK Input Hold time to SYSCLK SYSCLK High to Output Valid SYSCLK High to Output High-Impedance Min 2.5 0 0.5 0.5 6.0 6.0 Max Units ns ns ns ns
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Notes: 1. Maximum output propagation delays are measured with a 30pF load on the output. 2. Output Valid delay does not apply to DQM. Table 73 Symbol Ts Th Tp Tz Notes: 1. Maximum output propagation delays are measured with a 30pF load on the output. Table 74 Symbol Ts Th Tp Tz Tzb Notes: 1. Maximum output propagation delays are measured with a 20pF load on the output. - Connection Context Memory SSRAM Interface (Figure 67) Description Input Set-up time to SYSCLK Input Hold time to SYSCLK SYSCLK High to Output Valid SYSCLK High to Output High-Impedance SYSCLK High to Output Driven Min 3.5 0 0.5 0.5 0.5 6.5 6.5 Max Units ns ns ns ns ns - Chunk Buffer SDRAM Interface (Figure 67) Description Input Set-up time to SYSCLK Input Hold time to SYSCLK SYSCLK High to Output Valid SYSCLK High to Output High-Impedance Min 2.5 0 0.5 0.5 6.0 6.0 Max Units ns ns ns ns
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17.7 JTAG Timing Table 75 Symbol - JTAG Port Interface (Figure 68) Description TCK Frequency TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO Notes: 1. Maximum output propagation delays are measured with a 50pF load on the output. Figure 68 - JTAG Port Interface Timing TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid 40 50 50 50 50 2 50 Min Max 1 60 Units MHz % ns ns ns ns ns
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
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18 ORDERING AND THERMAL INFORMATION Table 76 PART NO. PM7388 Table 77 PART NO. PM7388 Table 78 PM7388 Table 79 - FREEDM-336A1024 Ordering Information DESCRIPTION 520 Enhanced Ball Grid Array (SBGA) - FREEDM-336A1024 Theta Jc AMBIENT TEMPERATURE -40C to +85C - FREEDM-336A1024 Junction Temp Maximum Junction Temperature for Long Term Reliability - FREEDM-336A1024 Theta Ja vs. Airflow
Forced Air (Linear Feet per Minute) Conv 15.0 8.4 100 12.9 7.6 200 11.5 7.1 300 10.7 6.8 400 10.3 6.6 500 10.2 6.4
Theta Jc 1 C/W
105 C
Theta JA @ specified power Dense Board JEDEC Board
Notes on Theta Ja vs. Airflow: 1. Dense Board - Board with 3x3 array of the same device with spacing of 4mm between device. 6 layer board (3 signal layers, 3 power layers). Chart represents device in the center of the array. Chart represents values obtained through simulation. 2. JEDEC Board - Single component on a board. 4 layer board (2 signal layers, 2 power layers), metallization length x width = 94 mm x 94 mm. Board dimension = 114mmx142mm. JEDEC Measurement as per EIA/GESD51
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19 520 PIN SBGA - 40 X 40 MM BODY Figure 69
A1 BALL CORN ER
- 520 Pin Enhanced Ball Grid Array (SBGA)
a aa
(4X)
0.30 M 0 .1 0 M B CAB C
A
D
D1, M b
31 30 29 28 27 26 25 24 23 22 20 21 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL 15
A1 BALL CO RNER
A1 BA LL ID INK M ARK
s E
E1, N
A e
s
e A
TO P VIEW
A A2
EXTE NT O F EN CAPSULAT IO N
BO TT OM VIEW
b bb C
C
ddd C
0.20 M IN
A1
SEAT IN G PLANE
SIDE VIEW
ALL DIM EN SIO NS IN M ILLIM ET ER . DIM ENSION aaa D EN O T ES PACKAG E B ODY P RO FILE. DIM ENS IO N bbb DE NO TE S PARALLEL. DIM ENSIO N ccc DENO TES F LAT NE SS. DIM ENSION ddd DENO TES CO PLA NARIT Y.
d
cc c
C
NO TES: 1) 2) 3) 4) 5)
A-A SE CT ION VIEW
PACK AGE TYP E : 520 THERM ALLY ENHANCED BALL G RID ARRAY - SBGA BODY S IZE : 40 x 40 x 1.54 M M Dim . Min. Nom . Max. A
1.30 1.51 1.70
A1
0.50 0.60 0.70
A2
D
D1
E
E1
M,N
b
0.60
d
0.5 -
e
1.27 -
aaa bbb ccc
0.20 0.25 0.20
ddd
0.80 39.90 38.00 39.90 38.00
0.91 40.00 38.10 40.00 38.10 31x31 0.75 1.00 40.10 38.20 40.10 38.20 0.90
0.20
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NOTES:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. FREEDM is a trademark of PMC-Sierra, Inc. The technology discussed is protected by one or more of the following Patents: U.S. Patent Nos. 5,640,398, 6,188,699 and 6,333,935 Can. Patent No. 2,161,921 Relevant patent applications and other patents may also exist. (c) 2002 PMC-Sierra, Inc. PMC-1991476 (R7) Issue date: February 2002
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. FREEDM is a trademark of PMC-Sierra, Inc. The technology discussed is protected by one or more of the following Patents: U.S. Patent Nos. 5,640,398, 6,188,699 and 6,333,935 Can. Patent No. 2,161,921 Relevant patent applications and other patents may also exist. (c) 2002 PMC-Sierra, Inc. PMC-1991476 (R7) Issue date: February 2002

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